Development of a verification IP for an I2C target device using UVM

In the complex process of designing an Integrated Circuit, verification has gained over time greater importance as technology node shrinks allowing electronic devices to support more functionalities having as consequences an added circuit complexity and cost of the chip. To reduce the possibility of costly bugs affecting the behavior of an integrated circuit, modular and reusable verification methodologies are adopted since the very first phase of the design: among these, UVM is nowadays the preferred one when performing functional verification. Crucial part of an integrated circuit are its interfaces with the outside world, which can be other chips on the same board, or sensors or external devices. Standard protocols have been invented to ease the configuration of the devices and the communication between them, such as USB, SPI, I2C. This thesis, which is the product of an internship with STMicroelectronics, illustrates the development of a verification intellectual property for an I2C target usingthe UVM methodology.