Improving Load/Store Queues efficiency

Modern microprocessors exploit Out-of-Order (OoO) execution to address the "memory wall" and enhance performance by increasing the number of instructions executed at the same time. The implementation of this technique requires the introduction of specific structures, the Load and Store Queues (LSQs), to buffer load and store instructions and ensure the memory is updated in program order, despite OoO execution. Increasing the number of in-flight instructions implies scaling up LSQs and the logic necessary to detect and resolve memory order violations, making these structures a bottleneck in terms of both power and latency. The goal of this thesis is the investigation of new techniques to reduce LSQs power consumption in next-generation Arm microprocessors. This is achieved not by evaluating alternative structures for LSQs, but by optimizing the operations performed by the current ones. The focus is primarily on introducing prediction mechanisms to filter out operations that identify and resolve memory dependencies, while maintaining the expected level of performance. This document presents, at first, the state of the art of LSQs and the methodology followed to identify inefficiencies and possible improvements for these structures. Then, each one of the considered optimizations is illustrated by detailing the investigation that introduced the idea, the implementation at Register Transfer Level and the challenges faced. Furthermore, the impact in terms of power, performance and area is evaluated to have an overall view of the obtained results. In the end, some final considerations are collected together with ideas for future work and improvements.