A Methodology for Power Estimation Early in the Design Phase based on a Mathematical Model and its High-Level Synthesis

Nowadays ASICs are present in any device around us, this trend will increase as IoT becomes more widespread. Chip complexity is increasing and time to market is shrinking, this leads to new challenges for silicon engineers, requiring designers to spend 6 to 8 months on design cycle. Reduction in design time can only occur if new design flows are identified, which allow identification of the power-performance-area (PPA) space at an early stage of the design. Misjudgment at a late stage of the project is not permissible and would lead to project failure. This thesis work identifies a design flow that allows estimating power consumption during the architectural derivation of digital IPs, enabling architectural corrections to be made before even writing a line of HDL code. In addition, the identified design flow, allows for reports and documentation of the designed IPs through the use of tools, avoiding hand-writing by the designer and saving valuable time. My experience at STMicroelectronics gave me the opportunity to understand the real issues in designing highly complex integrated circuits and to follow the development of an ASIC for mobile applications from customer requirements to tape out. During this activity, I noticed that a recurring problem was underestimation of chip power consumption. The identified flow allowed for sufficiently accurate power estimates at a stage when the IP architecture could still be modified. The obtained results have shown that the RTL-level power estimation performed on a high-level mathematical model of the digital IP to be designed is quite accurate, in particular the estimation with activity data is very close to the signoff.