In microelectronics, the front-end-of-line (FEOL) of integrated circuits has played a central role for many years, and research has pushed the performance well beyond expectations. However, the increase of the number of devices per unit area has put at serious disadvantage the back-end-of-line (BEOL), and this is undermining the performance of current/future technology nodes. More devices require more interconnects with tighter line-gap periods or pitch. Resistance and capacitance are both affected because of smaller and closer lines, and these are directly responsible for interconnect delay. In this work, an optimized resistance breakdown of a Power Delivery Network (PDN) is addressed to estimate the real impact of vias and lines on IR-drop.