Design, Verification and Integration of a hardware accelerator for image composition through alpha blending

The goal of this work is to present the development phases of a hardware accelerator for image processing. This accelerator has been created to implement the alpha blending technique, thanks to which it is possible to superimpose two images using the transparency channel called alpha. The accelerator was thought to extend the functionalities of a DMA controller that can exploit it to perform simple elaborations while moving data. The work will focus on the logical design phase, where the accelerator will be analyzed in terms of internal structure. The correct functioning of the accelerator has been tested using a UVM environment to prove that the design specifications have been met. On a second time, it has been tested using a system-level environment to perform actual tests written in C language that involve authentic images.