SystemC Transaction Level Modeling of an ASIC CAN controller and simulation performances comparison with an RTL model in VHDL

The main goal of the thesis work is to verify some of the improvements brought by an innovative digital system modelling approach, SystemC Transaction Level Modelling, which is based on the abstraction of intermodule communication from the architectural details of the functional units and the communication protocols. The parameter under verification is the simulation performance of the behavioural model of a CAN controller peripheral device, described in SystemC TLM1.0, with respect to a CAN controller described in VHDL. In order to obtain a valid comparison of the simulation times it is needed to have two devices with the same design complexity; therefore, the two versions are similarly described, namely they have the same external interfaces, they include the same type of sub modules and their main threads, managing the frame transmission, reception and processing, have similar body structures. Each of the two modules is tested by a functional testbench, performing a determined amount of frame transmissions between two CAN nodes and verifying the correctness of each transmission by collecting the processed frames from the receiving node. Thus, the test applied on the TLM device and on the VHDL benchmark are the same and they run on a common server, in order to measure the simulation performance in terms of the amount of real time corresponding to the same simulation time interval.