Exploring the digital-on-top-approach in an analog-oriented design implementation flow. The case of motion MEMS sensors

Today, MEMS sensors are rising in popularity as the application fields where they can be utilized is growing faster and faster. Their utilization ranges from consumer electronics and IoT to medical and military applications. MEMS rise to prominence is linked to its tiny dimensions and small power draw thanks to the miniaturization that characterizes them. Their extensive use in the whole electronics world in recent years has generated notable interest in developing sensors with increasingly high performance, with regards to accuracy, power consumption and data transfer speed to communicate with the central processing unit. This increase in the required transfer speeds means more control and optimization capabilities required for the implementation of timing sensitive components in the sensor, i.e., the digital core and the analog circuitry that interfaces it with the communication bus. The analog-on-top approach implies that the core logic is implemented using the digital implementation tools and then imported in the analog top level environment as a macro. With this method, the digital core is constrained using possibly not very accurate budgeting, and the total delay of the critical path is determined with a combination of transistor level simulations for the analog components and STA results from the digital environment for the digital core. This does not accurately reflect the timing of the real design since the real boundary conditions between analog and digital domains will differ from the budgeting done when constraining the digital core and the conditions used for transistor level simulations. A digital-on-top approach brings also area savings compared to the analog-on-top approach, since in the latter the so-called \textit{channel-style routing} requires extra area to route interconnections where no cells are placed, while using the digital implementation tools it is possible to route all the interconnects above placed cells while optimizing routing to minimize timing and cross-talk. In order to optimize the design of a six-axis motion sensor compatible with the I3C high speed protocol, the implementation with a digital-on-top flow has been explored. The d-o-t approach provides the ability to include the analog timing sensitive components in the digital design environment, making it possible to analyze the whole path with static timing analysis tools. This allows the digital design tools to optimize the design accordingly, without treating the analog part as a black box with a fixed, conservative delay. The whole implementation flow has been covered to troubleshoot the process and streamline the adoption of the d-o-t flow in mainstream products, and accurate timing metrics for the I3C related critical paths have been obtained, to evaluate the actual performances of the design and fully optimize it in the digital environment.