High Throughput Turbo-Decoders: Concurrent-PMAP and High-Radix Exploration

In digital communications, the throughput demand is rapidly increasing through years. Since modern standards have already reached throughputs above 1 Gb/s, it is expected, in the following years, to reach requirements up to 1 Tb/s. Channel-Coding is a fundamental technique employed in communication links, in order to identify and correct errors. Therefore, it should be adapted aiming to support the near future throughput requirements. Turbo-Codes are a promising choice in this scenario, due to their capability to work close to the Shannon's Limit. Therefore, the suitability of Turbo-Decoder architectures is object of study. Focusing on Turbo-Decoders, this work is proving how high degrees of parallelization are necessary to satisfy the discussed data-rate requirements. Therefore, a detailed study on the Concurrent-PMAP architecture, implemented on different radix-orders, is proposed. The aim is to highlight guidelines to select area efficient implementations, capable to push throughputs toward the next-future demand. The results are showing how the presented architecture is a valid candidate for high-throughputs, considering radix-2 and radix-4 implementations. Moreover, a general approach to develop a comparison model between architectures is detailed, aiming to speed-up the selection process among new proposed solutions.