Design of configurable Fault Folerant RISC-V Instruction Fetch and automatization through Travulog templates

The miniaturization of the microelectronic components together with the use of integrated circuits in increasingly more applications lead to an increasing use of Fault Tolerant (FT) systems. For this reason new techniques are required to automatize the transformation of systems from base to FT. This thesis investigates the automatic application of FT techniques inside the stage of a core written in SystemVerilog (SV). The aim of this project is to create a Toolchain able to apply different templates to an SV architecture in order to automatize the conversion of an architecture from base to Fault Tolerant. The templates are written in a new metalanguage called Travulog and they can be applied to an architecture using directly Python or HTravulog metalanguage inside the SystemVerilog. The Toolchain is used to convert the Instruction Fetch stage of the RISC-V cv32e40p to Fault Tolerant. Anyway the Toolchain can be used for whatever SystemVerilog architecture with the great advantage to be open source and extendible to new uses.