Verification, Identification and Elimination of parasitic structures in an integrated circuit to avoid unwanted triggering that could induce premature failures = Verification, Identification and Elimination of parasitic structures in an integrated circuit to avoid unwanted triggering that could induce premature failures.

This paper is related to the study of Latch Up (LU) phenomenon using TCAD simulation. It has been pointed out that latch up is a well-known phenomenon but questions remain about the sensitivity and interaction of different aggressors and victims. A complete silicon study would also consume too much resources as there are too many aggressor/victim combinations possible. The study was conducted in three stages. At first, results from a prior study were reviewed and simulation parameters were adjusted to match as close as possible these results. In addition, all possible aggressor – victim duos were simulated to be able to determine which combination should be protected in terms of LU. Protections, both standard and custom, were then added to the simulation in order to determine tendencies and verify the pertinence of said protections. Finally, a testchip was made with relevant combinations to be able to validate the simulation results on silicon.