On the analysis of DRAM faults on ANN applications

Testing hardware faults is a crucial step for the companies, since they can lead to failures that may impact on the dependability of their systems. Indeed, the companies invest money and time in order to test their hardware components, especially in safety-critical domain, such as automotive, robotic and avionic. Furthermore the companies must be compliant to various standards like the ISO 26262, an international standard for functional safety of electrical and/or electronic systems in serial production road vehicles. So there is a growing interest towards the development of new strategies for evaluating the dependability of safety-critical systems. In particular, the main focus of this thesis is to develop a framework that evaluates faults that may occur at the memory level. These faults can be of different nature, such as Single Bit Upsets (SBUs), stuck at bits, and block errors. The proposed framework mimics the behavior of a radiation beam in order to investigate the correlation between this radiation and the failures occurring within the memory device. It has been validated by using an Artificial Neural Network running on a hardware device that is simulated on Gem5. Gem5 is an architectural simulator used for computer system research at both architectural and microarchitectural levels. In my thesis, I developed two DRAMs models, similar to the ones used in the radiation campaign. These two memory devices contain different memory sections in order to isolate the source of error. Gem5 is configured using the System-call Emulation (SE) mode and a bare-metal approach, in order to be OS independent. The main benefits of the proposed framework are the following: it can be easily modified, allowing to simulate different systems; it is easy to change specific components or settings in order to mimic different real devices; finally, it is easily reproducible.