Testing hardware faults is a crucial step for the companies, since they can lead to failures that may impact on the dependability of their systems. Indeed, the companies invest money and time in order to test their hardware components, especially in safety-critical domain, such as automotive, robotic and avionic. Furthermore the companies must be compliant to various standards like the ISO 26262, an international standard for functional safety of electrical and/or electronic systems in serial production road vehicles. So there is a growing interest towards the development of new strategies for evaluating the dependability of safety-critical systems. In particular, the main focus of this thesis is to develop a framework that evaluates faults that may occur at the memory level.