Design of a fault tolerant RISC-V instruction execute stage for safety critical applications

Combining performances, power consumption and fault tolerance in modern integrated circuits is a real challenge. The goal of this work is to present a possible technique to detect and correct both transient and permanent errors in the execution unit of a RISC-V core, without affecting performances. TMR, Standby-Sparing, Alpha Counting and other techniques are mixed together to protect the ALU and the Mul-tiplier against single transient errors and multiple permanent errors. This technique can potentially be applied to any other critical compo-nent and its main advantage is that it allows the component affected by permanent fault to be reused in the remaining non-faulty subparts thus maximizing resources exploitation.