Design of FPGA-based TurboProduct Iterative Decoder basedon Polar Codes

Nowadays considering the large transmission infrastructures of data that travel at very high speeds, they must be transferred with considerable efficiency. Important results have been achieved almost at the limit of the maximum capacity of the transmission channel with different types of Error Correction Code (ECC), although they have never fully saturated it. Polar coding is a low-complexity channel coding method that can provably achieve Shannon’s channel capacity for any binary-input discrete memory-less channels (B-DMC). Apart from the theoretical interest in the subject, polar codes have attracted attention for their potential applications. Moreover, product codes are parallel concatenated codes usually used in optical communications for their good error correction performances and high throughputs, thanks to their parallelizable decoding process. In that master thesis, it has been illustrated a high throughput Turbo Product decoder for polar codes based on the Soft Cancellation algorithm decoding, which has been proposed in [5] which is an iterative message passing decoder, set on the Successive Cancellation classic schedule for the Decoding process of Polar Codes. The purpose is about to investigate on different parameter which the component decoder is based on and make them flexible compile-time and run-time, such as the number of iterations to refine the information or the number of processing element used in order to decoded the input data. Creating a larger set of parameter enlarge the solution space of performances, complexity and power consumption. The idea is to create a set of ideal parameter linked to the architecture to be variable in order to fit the required specification of performances and complexity.