A Top-Down Compiler for Spatially Distributed Computation of Convolutional Neural Networks

Convolutional Neural Networks (CNNs) are widely used in modern AI systems because of their superior accuracy, but they require highly parallel hardware structures to compute their operations efficiently. The computational complexity of convolution and the high amount of data movement are two key factors to be considered when designing a hardware accelerator for CNN. Systolic/Spatial architectures represent an interesting choice for accelerating the filtering operation of the convolution as they do not require stochastic data movement, but rather a regular and deterministic transfer and access. A good scheduling can exploit the deterministic CNN execution: in most deployment scenarios the neural networks do not change frequently, so a predetermined schedule would save many resource and control logic at runtime. A coherent and efficient Instruction Set Architecture (ISA) is required to maintain the flexibility of creating such schedules for different CNNs: it consists in some instructions that are necessary to cover the data movement and the logic required by a particular dataflow. The aim of this work is to develop, according to an offline compiler, a smart deployment of the instructions to the systolic array and investigating the possible implementations of such ISA on hardware architectures.