Performance optimization of an existing operational amplifier for new applications

The goal of this master thesis is the optimization of an existent Op-Amp, designed for high speed, in order to improve its precision and make it a good choice as differential amplifier for Texas Instruments next generation precision logarithmic amplifiers. The first objective is the increment of the amplifier’s capacitive load drive by a factor 10x to guarantee a minimum phase margin until 100pF. The second problem to be solved is the limitation of the short circuit current of the device to protect the inner circuit and the load connected to it. The third goal is the modification of the existent bias block, which from a dual CTAT/PTAT structure must be converted into a more compact all PTAT structure: this choice is justified by the impossibility to effectively use the CTAT circuit from the original bias block. Starting from a first theoretical approach, it has been possible to make all the proper changes to satisfy the requests. The final circuit has been simulated using Cadence® Virtuoso® over different corners and temperatures and the results are here presented.