Power dissipation and Energy consumption of digital circuits has emerged as an important design parameter in the evaluation of microelectronic circuits. This has led electronic architects to value Parallel Architectures that allow to perform many calculations, or the execution of processes, simultaneously: exploiting data parallelism reduces instruction bandwidth, reduces required memory bandwidth and lowers the power consumption. A classical example of this trend is the ‘Single Instruction, Multiple Data (SIMD)’ Instruction Set extension which is nowadays implemented in the majority of Instruction Set Architectures. Developing Parallel Architectures that can deliver good performance without the energy and design complexity of higly Out-of-Order superscalar processors is of great interest: Data-parallel applications have had a huge impact not only in highperformance scientific computing but in a diversity of domains such as financial analysis, data-processing, machine learning and many others.