Design and Integration of a Debug Unit for Heterogeneous System-on-Chip Architectures

The end of Dennard scaling in the past decade marked the crisis of constant power density scaling across different technology nodes. As a result, the Semiconductor Industry faced an increasing demand for power-efficient systems that promoted the transition from homogeneous to heterogeneous architectures. Heterogeneous systems couple general-purpose processors with a growing number of specialized hardware accelerators that can only execute a few tasks in a very efficient way. Academia put a significant effort in investigating architectures for several domain-specific accelerators and providing innovative solutions addressing the integration challenges in heterogeneous systems. In most of the cases, the ISA of the RISC-V project is leveraged for the processor cores of the platforms proposed. Among the existing implementations, the Embedded Scalable Platform (ESP) project developed at Columbia University plays a distinctive role. As opposed to other open source RISC-V platforms, ESP promotes a system-centric view based on the coupling of a modular socket-based architecture with a companion system level methodology. The goal of this approach is to relieve the designer from the burden of the IP integration process, by decoupling the IP design from the rest of the system. In ESP, each IP is integrated in a tile and connected to a scalable network-on-chip through a socket that implements a set of distributed platform services. These give the illusion of a traditional system to the external IP designer and software developer. At the same time, ESP promotes a shift of the engineering effort by moving the abstraction level from register-transfer level (RTL) specifications to a system-level viewpoint leveraging high-level-synthesis flows supported by many commercially available CAD tools. Several ESP instances capable of booting Linux have already been prototyped on different classes of FPGAs in the past decade. Starting from the existing ESP integration flow, an ongoing collaboration between Academia and Industry is currently aiming at the development of a companion agile flow for ASIC implementation that targets advanced technology nodes. In the context of chip manufacturing, pre-silicon verification and design for testability assume a fundamental role. My Master Thesis addresses some of the challenges related to the testing, debugging and verification of complex systems. Specifically, I developed a modular Debug Unit for the pre and post silicon unit test of IP blocks integrated in a heterogeneous system. The approach adopted in this work adapts well to the platform-based approach of ESP; in fact, my Debug Unit implements a new platform service that enables the independent test of every tile, decoupled from the system interconnect. Throughout the dissertation, I give a comprehensive overview of the steps involved in the design and integration of the Debug Unit in the system. First, the key requirements derived from the ASIC backend flow are considered. Then, the interaction of the testing logic with the surrounding environment is discussed in detail to show the challenges faced in the integration process. The results obtained shows that the Debug Unit offers the possibility of running tests on each ESP tile at all the stages of the design. This supports the thesis that design for testability (DFT) can be used to provide a general testing approach, not limited to ESP, to handle the increasing complexity of heterogeneous systems.