Study and development of a fully-digital peripheral designed to read capacitive sensors for structural health monitoring

The work documented in this thesis, in collaboration with STMicroelectronics, regards the study and development of a suitable solution to perform the reading of capacitive sensors for Structural Health Monitoring (SHM), which is a recent concept involving the periodical monitoring of structural parameters by relying completely on a distributed electronic system and not merely on human-dependent inspection. In particular, the final target of the designed interface is its integration as a peripheral into a System-on-Chip (SoC) currently under development at STMicroelectronics, containing at its core a proprietary microcontroller employing RISC-V open-source Instruction Set Architecture (ISA). After a focus on pressure sensors, an extensive literature research of possible signal conditioning interfaces for capacitive sensors is carried out in this thesis, with a conclusive comparison that recognizes the Iterative Delay-Chain Discharge (IDCD) technique as the most promising solution for the target of the project. Furthermore, an in-depth theoretical analysis of the state-of-the-art regarding IDCD-based Capacitance-to-Digital (C2D) interfaces is discussed, followed by a number of custom adjustments and the consequent development of a Register-Transfer-Level (RTL) design of a plausible implementation, which is the main contribution offered by this work. In order to experimentally demonstrate the functioning of such design, a hybrid Field-Programmable Gate Array (FPGA) & Printed Circuit Board (PCB) prototype is realized from scratch by exploiting Digilent's Arty A7-35T FPGA Development Board as the former and a custom-made circuit, fabricated at STMicroelectronics, as the latter. Behavioral simulations of the RTL design and the experimental characterization of the prototype are provided, suggesting the validity of the proposed C2D interface as a possible candidate for SHM. Finally, with the task of making the RTL design compatible with STMicroelectronics' SoC, an Advanced Peripheral Bus (APB) compatibility layer is developed and simulated to prove its correctness.