On the automatic generation of testing programs for embedded system = On the automatic generation of testing programs for embedded system

On the generation of a security oriented verification test set for embedded systems. Nowadays, the constant increasing of the design, development and integration for the circuits have become them a fundamental piece of the day to day, we found it inside simple systems as a building entrance to authenticate the people how arrive, or in more complex systems like cars, airplanes and other means of transport. All this new circuits are placed to develop a specific task aim to improve the well-being of the users and creating a more intuitive environment for the final users. Thanks to the integration and constant interaction between systems and users, now they are capable to provide users with the expected behavior for each task and avoiding being harmful in any unexpected malfunctioning, i.e, a reliable system that performs correctly at certain time. To achieve this goal, one of the main methods to avoid these issues is the testing at each phase of the system creation, in which the entire system is excited and check to certificate if the results are in line of what is expected. These systems are characterized by have, as principal units, a core in charge of the entire system management; this implies the control of the different peripherals, the data processing, the execution’s instructions and other tasks regarding the whole system execution. The cores, are generally composed by blocks and are created to develop a specific task. To test them there are several methods to trial the process, looking to generate all the possible scenarios in which the core will be involved. In this thesis, the testing process will be applied in an open source system called Pulpissimo which was developed as part of the PULP platform in collaboration between 2 universities, ETH Zurich and University of Bologna. This particular system is implemented as the main System-on-Chip controller for these platforms. Specifically, the SoC core was implemented with the use of a RISC-V based processor called RI5CY, an in order single core with 4 pipeline stages. For the testing will be performed a methodology on the SoC and will be evolve a technical analysis on the final results together with a statistic study of the behavior of this SoC when the method is applied.