System Level Test of Reliable ICs

In recent years, the increasing complexity of systems has led to new solutions for testing. According to Moore's Law, the number of transistors on a chip has grown up. Manufacturing costs are decreased with shrinking sizes. In spite of reducing manufacturer costs, the cost of the test remained the same. Hence, it occupies a considerable amount in the rate of total expenditure. Manufacturers cannot ignore testing despite the cost of the test since even the smallest errors can lead to significant safety issues. Testing is highly essential for the system's dependability, reliability and trustworthiness. Notably, in automotive systems, high dependability and safety are the key parameters. The new generation of self-driving cars has brought a fresh perpective that full safety automotive systems. Hence, automotive systems must undergo many tests and stress processes. Bernina Microcontroller is used in this thesis. Bernina is a new generation microcontroller, which is built on Power Architecture technology for automotive applications. Bernina Microcontroller belongs to an SPC5x family and is produced by STMicroelectronics. This project aims to determine faulty products and observe their errors and faults, which are marked correct under the appropriate stress conditions. System-Level Test is applied under the same stress conditions. System-Level Test is the best testing technique for mimicking the real working conditions of the products. Stress conditions mean that generating complex applications under the critical level of voltages or temperatures. Almost most programs use load/store instructions, i.e. accessibility of memory is a vital point in testing perspective. For that reason, March C memory test is implemented for single-core and multi-cores applications. It is essential to have the best fault coverage in a short duration of the test. Therefore, March C Algorithm is improved according to the Back-to-Back memory cycles. There are four main cases for the March C Algorithm. They are respectively: R0, (R0, W1), W0 and (R1, W0). All these cases are rewritten according to the unlooping technique. As a result, each cases test duration is decreased. In the thesis report, they are detailed with sample Assembly VLE code. Moreover, Data Cache and Instruction Cache are activated for reducing the test duration and increasing the complexity of test (increase the stress level). The end of the thesis work, after verification of simulations, all features are implemented to the real-time device, Bernina Hardware. To increase stress levels, another board, which is called Stealth, is programmed and is used for regulating to the Bernina Microcontroller. There is nothing available on the Internet about Bernina Microcontroller. Hence, that thesis report can be used as a guide book of Bernina and mini-manual of Bernina, especially for the architecture of Bernina Local Processor Core memories.