Relaxation Digital to Analog Converter: Analysis and Design

Emerging Internet of Things (IoT) applications require ultra-low voltage, reconfigurable, highly energy and power efficient integrated circuits (ICs) for sensing, computing and communicating, which are extremely challenging to be designed by traditional techniques. Interfaces towards the analog world, in particular, require medium-to-low resolution (8-12bit) data converters with a sample rate in the hundreds of kS/s range, capable to operate at supply voltages below 0.5V and achieving an energy figure of merit (FOM) in the order of 1fJ/(conversion step). In this framework, the thesis addresses the analysis and design in 40nm CMOS technology process of a Digital-to-Analog Converter (DAC) suitable to the challenges of IoT applications. The converter, based on the novel-in-concept relaxation digital-to-analog conversion technique, exploits the impulse response of a first order RC network to generate and sum up binary weighted voltages to perform D/A conversion. The followed approach begins with the theoretical analysis of the converter working principle, identifying non-idealities, modelling their effect on converter performance and developing design guidelines to minimize them. A set of configurations of the analog block has been chosen to explore the space of design solution and implemented within the 40nm PDK. Cadence simulations have been carried on the chosen configurations, initially driven by behavioural Verilog-A blocks and performed at the schematic level, allowing a complete formulation of a design strategy and compensation technique. Post layout simulations of the analog block follows, allowing to choose the better configuration solutions, converging to few final test-cases. Digital circuit which drives the converter and implements the compensation strategy has been designed in Verilog HDL code. After synthesis and layout generation has been performed for the digital blocks, the thesis is concluded by evaluating post-layout performance of the whole converter. The DAC presented in this work turns out to be a tiny, matching insensitive, almost fully-synthesizable architecture, allowing conversion rates up to MS/s with a state of the art energy figure of merit. Future developments include digital design optimization for further conversion energy enhancement, circuit fabrication and post-fabrication performance validation, insertion of the Relaxation digital-to-analog converter as a part of more complex systems which would take advantage of the presented topology features.