SLX FPGA: FAST FLOW TURN-AROUND TIME USING LIGHT PROFILING

SLX FPGA is one of the main products developed by Silexica to address, in an automatic way, the problem of sequential code optimization for parallel execution and Hardware/Software partitioning for FPGA-enabled SoCs. In other words, the input C/C++ user application is analyzed, identifying parallelization opportunities, optimized, distributing effectively the partitions in the available resources (CPU and FPGA), and compiled into the target, in order to achieve faster execution times. The first and probably the most important step carried out by the tool is the Analysis phase. Relying on sophisticated compiler technology, both static and dynamic analysis are performed to fully understand the user code and thus enable subsequent optimizations. The dynamic analysis is certainly the most interesting, as it provides information about the behavior of the application, but also the most expensive, as it requires to profile the application itself. The process of instrumenting, running and profiling the user code to trace the events of interest affects heavily the performance of the tool, resulting in a high turn-around time for big applications. The strategy introduced in this thesis tries to tackle this problem with a combination of "light" and "selective" instrumentation: the most recurrent events (e.g., accesses to variables) are dropped from tracing in a first analysis (light instrumentation) and then covered afterwards only for the functions of interest (selective instrumentation). This approach offers a faster profiling phase which still enables most of the features provided by the tool (e.g. call graph generation). Different use cases demonstrating the effectiveness of SLX FPGA in bringing a sequential C application to an heterogeneous platform (CPU+FPGA) as partitioned (between HW/SW) and accelerated version are finally presented.