Study of low power and radiation hard Design For Testability solutions for High Energy Physics applications

In Particle Physics, electronic systems are widely exploited to track and record collisions results: dedicated ASICs are used to read and analyse silicon sensors. The High Luminosity LHC phase requires the development of novel detectors for CMS Outer Tracker, able to perform real-time computations and to stand harsher conditions (-40°C, 100 Mrad of ionizing dose). The development stage of the three Front-End ASICs (MPA, SSA and CIC) is finalized and a successful verification phase will imply the large scale production. The limited manufacturing yield requires testing strategies to exclude defective units from being installed, guaranteeing their correct functionality. The aim of the thesis is to study and develop innovative procedures to replace the currently used functional tests, which present limited performances in terms of testing time, completeness and costs. The concept of structural test is introduced for the first time for ASICs in the field of High Energy Physics and Design For Testability (DFT) techniques are studied for a novel testing approach. The latter include circuit configurations and netlist modifications to ease testing procedures, and must be developed at the same time of the development of the chip. Two solutions have been studied and implemented, a Built-In Self-Test for memory blocks (mainly SRAMs) applying a March algorithm and the Scan Design, which allows to exploit the powerful structural algorithms. Considering the stringent constraints for the ASICs, particular attention was paid to radiation tolerance and power overhead, and studies have been carried out to assess the best trade-off between fault coverage and negative impacts on area and timing.