Muhammad Tahir Rafiq
Routing Congestion Tracing in High-Level Synthesis Flow of FPGA based Systems.
Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2019
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Abstract
In the modern day digital electronics, logic synthesis that starts from an RTL description of design has been the dominant method to implement digital systems on both FPGAs and application specific chips. But in the recent times, High-Level Synthesis (HLS) has become the preferred choice of hardware designers and engineers for implementing complex digital designs. State of the art EDA flows have also incorporated HLS based design techniques. High-Level Synthesis or HLS is an automated process that accepts synthesizable code written using high-level languages e.g. C, C++, SystemC and OpenCL (Open Computing Language) and transforms them to RTL level designs. This design is then implemented on hardware devices e.g.
FPGAs
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