Routing Congestion Tracing in High-Level Synthesis Flow of FPGA based Systems

In the modern day digital electronics, logic synthesis that starts from an RTL description of design has been the dominant method to implement digital systems on both FPGAs and application specific chips. But in the recent times, High-Level Synthesis (HLS) has become the preferred choice of hardware designers and engineers for implementing complex digital designs. State of the art EDA flows have also incorporated HLS based design techniques. High-Level Synthesis or HLS is an automated process that accepts synthesizable code written using high-level languages e.g. C, C++, SystemC and OpenCL (Open Computing Language) and transforms them to RTL level designs. This design is then implemented on hardware devices e.g. FPGAs. FPGAs have limited hardware resources in terms of logic cells, and interconnects that contain wires that are routed to implement power supply, clock and signal nets. During the routing process in the design implementation flow, congestion is generated if resource utilization is high or the design is very complex. This routing congestion forces router to detour the tracks thus increasing the clock period and in some cases the tool is even unable to route the design and the implementation process fails. This situation leads to difficult timing closure of design and longer design cycles. Error messages and reports that indicate routing congestion contain information only about the congested cells and congestion windows. Unfortunately there is no simple traceable link available that can help designer comprehend what section of high level code is the main source of this routing congestion. Design tools like Xilinx Vivado Design Suite contain some information to avoid congestion but it is more relevant to the RTL descriptions and is focused on iterative patterns of RTL design cycles to alleviate congestion. Congestion report generated by Vivado indicates enormous number of complex RTL net names that are automatically assigned to the nets during HLS and that are responsible for the congestion present in the design. Although present in the auto-generated RTL descriptions of design, these complex net names are not explicitly related with the high level instructions responsible for the creation of these nets. The main aim of this research work is to analyze the routing congestion phenomena in FPGAs and to generate a correlation between the HLS code and the congested nets and windows information reported by Vivado Design Suite during the placement and implementation phase of design flow. A novel technique has been devised that collects data generated by the tools in various files during design flow and the result is correlation information between high level code and the congested windows on FPGA. This correlation information indicates the specific high level instructions responsible for routing congestion in a quantitative manner, and is very handy for designer in avoiding congestion in early design stages without digging deeply into the auto generated complex RTL descriptions of designs. Based on this high-level congestion information, some counter measures like modifying the source code without losing functionality and efficiency of design and the use of some suitable HLS directives, are also proposed in the end. The effectiveness of this technique is demonstrated using a Complex Discrete Fourier Transform Design to eliminate congestion at the C++ source level.