i.MX8 Verification Flow and Environment =

Functional verification has long been a major concern in digital design. Over the years, the huge investment in verification spurred the development of tools and methodologies for systematic and cost-effective solutions. In particular, the verification environment covers a fundamental role in the process since it collects the results of the tests to extract more valuable information about the verification closure of the design. The proposed flow is based on vManager tool of Cadence and supports all the phases of the System-On-Chip (SoC) verification process from the functional test up to the RTL freeze and final Tape-Out. The new methodology is designed to be a complementary module for the current verification environment, to cover those flaws still affecting the verification process. The first part of the thesis contains an overview of the verification process, with a focus on the methodologies and techniques applied at each stage. Moreover, a brief introduction to the most relevant information on the architecture of the DUT is presented. The second part instead provides an analysis of the current verification environment high- lighting the critical issues. To solve the problematics, two different approaches are presented. The former proposes some improvements to the environment without changing the tools used for the verification. The latter instead implements a completely new flow based on vManager tool. Finally the last part presents the results and improvements achieved with both the approaches, together with the main problematics still open.