Advanced SDRAM controller architecture for Approximate Computing

Dynamic random-access memory (DRAM) refresh operations waste energy and degrade system performances. Most cells can retain their data for a time longer than the actual CBR refresh used in modern chips. By knowing cell retention times, it's possible to group DRAM rows into retention times bins and apply different refresh rates at each row. The basic idea is similar to "Retention-Aware Intelligent DRAM Refresh" implementation known in literature as "RAIDR" , where in a system with 32 GB DRAM achieves 74.6 % refresh reduction, an average DRAM power saving of 16.1 % and an average system performance improvement of 8.6 % at the cost of a storage overhead. In terms of architecture, instead, it's quite similar to "Smart Refresh" solution proposed by Ghosh and Lee. Basically, DRAM cells of modern chips show a retention time that extends approximately from 1 to 6 seconds at room temperature (till 45 °C), making most of refreshes unnecessary. In fact, so such short refresh interval takes into account an increase of temperature up to 85 °C, where cells retention time decreases exponentially. So the realized architecure first performs an initial profiling of the actual retention times of each row and fills two SRAMs: the first stores the thresholds corresponding to the retention times of each row, the second the counters related to each row. An experimental study has been conducted first, finding that the pattern that allows to obtain the best coverage of bit failures is the quasi dynamic pseudo-random one (thanks to the usage of two LFSRs to obtain different data on each row): this is in agreement with previous works where dynamic random patterns, especially in high capacity and complex memory architectures, guarantee the best coverage. Simuations are performed in repeated rounds separated by the same time delay: this, indeed, frees the analysis from “Data Pattern Dependance” (DPD) issue. Once obtained the entire characterization of the memory, each row will be refreshed according to its worst case cell: in fact, a refresh operation is merely a sequence of an “ACTIVE” (ACT) command followed by a “PRECHARGE” (PRE) command, provided that the bitlines are precharged first. So whenever each row counter elapses, the modified controller issues a sequence of these two commands to refresh that row. This, as known, could be expensive in terms of activating each single row issuing RAS-only refreshes but, if the distribution of the retention times is similiar to the one mentioned in previous experimental works, one could achieve considerable power savings and refresh overhead reductions at the cost of an increase of the controller's area, without doing any modification to the DRAM itself or to its protocol. For the 512 Mb SDRAM used in the designed FPGA-based platform, the storage overhead is of about 32 KB for 4-bits counters (0.2 % of the used SDRAM bank capacity). Moreover, an access to a row (reading or writing) restores the content like a refresh does, then in this case the counter is reset to its maximum value: in applications with dense accesses, then, further refresh overhead reductions are achieved. Secondly, a “Selective Row Granular Refresh” (S-RGR) feature has been introduced to skip refreshes on some of the rows at the maximum sustained retention time. In 16 refresh cycles, the refresh overhead reduction could be up to 75 % compared to Auto-Refresh, that means increased performances and reduced power consumptions.