Dynamic random-access memory (DRAM) refresh operations waste energy and degrade system performances. Most cells can retain their data for a time longer than the actual CBR refresh used in modern chips. By knowing cell retention times, it's possible to group DRAM rows into retention times bins and apply different refresh rates at each row. The basic idea is similar to "Retention-Aware Intelligent DRAM Refresh" implementation known in literature as "RAIDR" , where in a system with 32 GB DRAM achieves 74.6 % refresh reduction, an average DRAM power saving of 16.1 % and an average system performance improvement of 8.6 % at the cost of a storage overhead.