Using Arm’s vector extensions for network infrastructure

To leverage data-level parallelism at the instruction level, algorithms for signal processing like the Fast Fourier Transform have been implemented using SIMD extensions. For the Arm processor family, the SIMD instructions are part of the NEON architecture extension. The introduction of the Scalable Vector Extension (SVE) in the Armv8-A architecture has significantly enhanced the vector processing capabilities. The next generation is coming and it will be known as SVE2. One of the key area for Arm is the speedup of the networking architectures at the physical layer. Thus, in this thesis the implementation and the performance of algorithms that utilize the three Arm's vector extensions have been investigated. To determine their efficiency, a software implementation of the LTE protocol stack known as OpenAirInterface has been used as a reference. The measurements obtained for the next generation vector extensions will be used to provide improvement proposals for the future hardware. The organization of the work is the following: the first chapter introduces the basic notions of LTE, OpenAirInterface and the vector extensions of Arm; the second chapter describes the methodology that has been applied and the out-of-the-box measurements obtained on an Arm processor; the third chapter shows the benefits obtained by using the NEON vector extension, in terms of cycle count reductions; the fourth chapter is investigating the improvements that could be possible to obtain in the next generation architecture with SVE and SVE2 that have been measured on a simulator; the fifth chapter is the conclusion, with some final remarks and future work propositions.