Modeling of Tunnel-FETs: accurate calibration of numerical and semi-analytical models

Making transistors smaller is a process called transistor scaling and it has been the most important factor in increasing a computer’s computational power, speed, and memory. Indeed, the smaller transistors are, the more they can be integrated into a chip, which will feature more complex functions. This has been clear since the beginning of electronics, the reason why great efforts have been made on miniaturization. This idea led Gordon Moore to predict in 1975 that the number of transistors in a dense integrated circuit (IC) would double every two years. This prediction, driven by transistors size reduction, has come true ever since it was made, so it became the so-called Moore’s law. However, the miniaturization process is now reaching its limits due to the increasing difficulties of silicon and voltage supply scaling. Nowadays, transistors are still getting faster generation-to-generation but not at the same rate as was achieved in the 90s, since the primary emphasis in transistor design has shifted from speed to limiting power consumption. A crucial path in reducing power consumption is reducing the supply voltage V_DD since the dynamic power consumption of a transistor in the ON state, and the power dissipated by a transistor in the OFF state are proportional to the square and the first power of V_DD, respectively. At the same time, the overdrive factor (V_DD−V_TH) must remain high to achieve a sufficient I_ON, which poses constraints on V_TH, that must be lowered. But the V_TH reduction means an exponential increase of I_OFF, which is unacceptable. One way to overcome these problems is to use devices with small subthreshold swings (S), allowing current to decrease rapidly as the gate voltage is lowered, providing smaller I_OFF. A device with a steep slope, which means having a small S, can operate with low V_DD and low V_TH, while still retaining a low I_OFF, which is paramount in today’s nanoelectronics. One of the most promising devices featured with steep slopes is the Tunnel-FET (TFET): its accurate modeling is important to allow device optimization and circuit design, the reason why they are the topic of this work. More in detail, this work is focused on the study and comparison of double gate TFETs with two different approaches: one is semi-analytical, implemented in Matlab, and the other is numerical and is carried out with the commercial TCAD simulator Synopsys Sentaurus Device. The semi-analytical approach computes the current with the Landauer-Büttiker formula, adapted to tunneling processes. One of the main ingredients of the Landauer-Büttiker formula is the transmission probability T which gives the probability of having tunneling of electrons and holes between the bands of a TFET. T is expressed by a semi-classical WKB (Wentzel, Kramers, Brillouin) approximation. Concerning the numerical model, the dynamic nonlocal path band-to-band tunneling model is used. The TCAD is based on a completely different approach since the contribution of tunneling to the current is expressed in terms of electrons and holes generation-recombination rates. In this work, TFETs based both on direct and indirect tunneling mechanisms are studied, and the calibration procedures of the fitting parameters of the numerical and semi-analytical models are reported. The semi-analytic approach can model the TFET with both gate voltage polarities, and it takes into account several physical phenomena, such that accurate comparisons can be made with the TCAD.