3D co-integration of memory and logic components for In-Memory Computing applications

The MY-Cube project aims at fabricating a 3D cube composed of a stack of 1T1R structures, and to perform logic operations inside. this could allow for a drastic reduction of power consumption of integrated circuits. A first part of this internship is dedicated to the analysis of TCAD simulations of the employed access transistor, the JunctionLess Transistor. The transistor physics was explained, the influence of the parameters over the performances investigated, and different conditions for which the transistor meets the requirements of an access transistor determined. A second part is dedicated to the SPICE simulation of circuits performing In-Memory Computing operations. Several circuits inspired from the literature has been simulated, optimized, design rules have been provided and their intehration into the cube has been discussed. This internship took place at the very beginning of the MY-Cube project. It allowed for an understanding of the transistor and provided methods to optimize its performances. It also provided an overview of what is possible to do in term of In-Memory Computing circuits using Ox-RAM.