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Study, design and synthesis of a regular structure for logical function computations

Lara Tovar, Bryan Dario

Study, design and synthesis of a regular structure for logical function computations.

Rel. Edgar Ernesto Sanchez Sanchez. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2018

Abstract:

This research work proposes an innovative model for logical functions computation using an approach that concerns a regular (highly structurally similar) design in a structure based on Cellular Automata (CA) and the architectural principles of a programmable cellular array. Similar to CA such structure possesses local connectivity in neighborhoods defined by columns (also defined as layers) of cells, as well as same functional rule in all cells in a column. Different from conventional CA, such as those extensively studies by Steven Wolfram [Wolfram, S. "Theory and Applications of Cellular Automata (Including Selected Papers 1983–1986)", [Wolfram, S. (Ed.)]. Advanced Series on Complex Systems 1. World Scientific Publishing, 1986] [Wolfram, S. "A new kind of science", Champaign, IL: Wolfram Media. 2002.] only certain cells in a neighborhood contribute to processing; cells in a subsequent layer allow rerouting of information, and consequently, subsequent layers implement further Boolean functions. Therefore, the thorough choice of rules, which are the exact same per each layer, enables an efficient, and for the first time, single CA layer implementation of basic logic functions. In a corresponding programmable device, within each layer (e.g. associated with a column and a rule) and, as a result, within each time quanta, or clock cycle, one is able to perform conventional logic functions and additional multi-bits operations. Complex processing can take place over multi-layer computing. This thesis work presents a layer reconfiguration mechanism that offers an architecture of a Field Programmable Cellular Array (on-going patent procedure) whose designs use similar cell rule per layer trading unwanted use of resources in number of gates logic functions for regular and constant design. This thesis work illustrates the implementation of basic logical functions of multi-bit processing, and the operations associated with Arithmetic Logic Units.

Relators: Edgar Ernesto Sanchez Sanchez
Academic year: 2018/19
Publication type: Electronic
Number of Pages: 76
Additional Information: Tesi secretata. Fulltext non presente
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: JET PROPULSION LAORATORY/NASA - 4800 oak Grove Drive, Pasadena, CA 91109, U.S.A. (STATI UNITI D'AMERICA)
Aziende collaboratrici: Nasa's Jet Propulsion Laboratory
URI: http://webthesis.biblio.polito.it/id/eprint/9979
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