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Design of an integrated DC-DC boost converter for portable biomedical devices

Fabio Bertini

Design of an integrated DC-DC boost converter for portable biomedical devices.

Rel. Gianluca Setti. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2018

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In the near past technology progress enabled electronic circuits to become smaller and denser. Moreover, scaling down of Integrated Circuits (ICs) fabrication processes allowed for the reduction of the supply voltage and techniques for diminishing power consumption were developed. As a consequence the use of battery-powered portable devices has grown rapidly and power electronics had to expand its coverage to permit their realization. Compact, cheap and efficient monolithycally integrated converters are of paramount importance for portability and performances need to be improved continuously, with growing challenges and problems. Smartphones, laptops, remote sensors and controllers are just few examples of applications made possible by integration and technology progress. However, also new possibilities for enhancing directly people’s life opened. One of the most interesting, attractive and fascinating is the development of biomedical implantable devices: they permit to monitor health constantly and to be a help for people’s handicaps or even a substitute for physical lacks, such as limbs amputations. The objective of this thesis is to design a power converter able to supply a portable neural stimulator, whose aim is to tackle obesity by providing patient’s appetite control. It has been carried out in its entirely at the Centre for Bio- Inspired Technology, Imperial College London, (UK), within the i2MOVE research group. The main challenge is the contemporaneous fulfillment of system reliability, high power conversion efficiency and compactness of the device. Overall, the whole project is based on a top-down approach, including all the design steps of a real IC, with the exception of the layout generation. A preliminary analysis involves a quick literature review, the choice of the correct topology, based on technical specifications, and the high-level block scheme definition of the system. Then a complete description of each block is provided with a Hardware Description Language (HDL), specifically Verilog-AMS. Afterwards, simulations are carried out to verify the correct behavior of the entire system. Finally, each HDL block is translated into an equivalent transistor-level schematic and everything is simulated again to confirm proper functionality. The software used for the design is Cadence Virtuoso©, although MATLAB© is exploited as well in the preliminary phase.

Relators: Gianluca Setti
Academic year: 2018/19
Publication type: Electronic
Number of Pages: 110
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: Imperial College London (REGNO UNITO)
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/9572
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