Politecnico di Torino (logo)

Validation and test of SoC devices

Alessandro Ciraci

Validation and test of SoC devices.

Rel. Matteo Sonza Reorda, Edgar Ernesto Sanchez Sanchez. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2018

PDF (Tesi_di_laurea) - Tesi
Licenza: Creative Commons Attribution Non-commercial No Derivatives.

Download (698kB) | Preview

Validation and test of SoC devices - Abstract Design validation and testing are two of the most important and time consuming phases of the development of a modern IC. Validation is aimed at verifying that the designed circuit doesn’t violate any requirement and it has the specified behaviour. Hardware testing is instead aimed at detecting faults in the physical die due to manufacturing defects; an important metric to judge the quality of a hardware test is the fault coverage, which is the percentage of faults detected by the test. Hence these two steps are required to ensure the proper functionality of any integrated circuit. This thesis explores the use of a functional test, in this case a set of software applications, to perform a hardware test, analysing coverage figures on selected parts of the SoC the software is running on. All these tests and analysis are performed via an HDL simulator, loading the bitfile of the application onto the main memory and “executing” the software in the simulated system. Since the simulator doesn’t evaluate fault coverage, test quality has been evaluated through the closes metric available: toggle coverage. This figure represents the percentage of transitions that have occurred on all nets inside the design. The System-on-Chip used throughout this thesis is the LEON3 by Cobham Gaisler. Software has been generated using the RCC 1.3 cross-compiler environment, also provided by Cobham Gaisler, that includes a customised GCC compiler and the LEON3 RTEMS RTOS libraries. The application developed provides a functional test for one of the UART peripherals of the LEON3 SoC. This application starts by booting up the system, also configuring the UART peripheral. Then it starts a series of transmissions, designed in such a way to maximise the utilization of the transmission logic. This data gets captured by an external block and, at the end of the transmissions, sends it all back, injecting also some errors to improve coverage on the receiver side of the peripheral.

Relators: Matteo Sonza Reorda, Edgar Ernesto Sanchez Sanchez
Academic year: 2018/19
Publication type: Electronic
Number of Pages: 60
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/9496
Modify record (reserved for operators) Modify record (reserved for operators)