Study and development of a new Fault Simulator for the new generation of European FPGA

Alessandro Di Chiara

Study and development of a new Fault Simulator for the new generation of European FPGA.

Rel. Luca Sterpone. Politecnico di Torino, Master of science program in Computer Engineering, 2017

Development of a new Fault Simulator for the New Generation of European FPGA

2017/18

Electronic

Tesi secretata. Full text non presente

Master of science program in Computer Engineering

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