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Study and development of a new Fault Simulator for the new generation of European FPGA

Alessandro Di Chiara

Study and development of a new Fault Simulator for the new generation of European FPGA.

Rel. Luca Sterpone. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2017

Abstract:

Development of a new Fault Simulator for the New Generation of European FPGA
Relators: Luca Sterpone
Academic year: 2017/18
Publication type: Electronic
Number of Pages: 64
Additional Information: Tesi secretata. Full text non presente
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/6612
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