m255
K4
z2
!s11e MIXED_VERSIONS
!s11f vlog 2020.1 2020.02, Feb 28 2020
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 dC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/simulation/modelsim
Emyaltpll
Z1 w1595154308
Z2 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
Z3 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
!i122 2
R0
Z4 8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/myaltpll.vhd
Z5 FC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/myaltpll.vhd
l0
L43 1
VmD^LQoNjGVPR6lF[G`kY;1
!s100 Q9RDKgSbO>[g`E9SD14Sc0
Z6 OV;C;2020.1;71
31
Z7 !s110 1738765835
!i10b 1
Z8 !s108 1738765835.000000
Z9 !s90 -reportprogress|300|-93|-work|work|C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/myaltpll.vhd|
Z10 !s107 C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/myaltpll.vhd|
!i113 1
Z11 o-93 -work work
Z12 tExplicit 1 CvgOpt 0
Asyn
R2
R3
DEx4 work 8 myaltpll 0 22 mD^LQoNjGVPR6lF[G`kY;1
!i122 2
l132
L54 155
VG]a1[]M_2z?_B30`C]bEC2
!s100 T[=n[A>ih;k?Ie]a^0RMH2
R6
31
R7
!i10b 1
R8
R9
R10
!i113 1
R11
R12
vmyAltPll_altpll
!s110 1738765832
!i10b 1
!s100 U>^b0U>E7U5X`41EndATc1
!s11b Dg1SIo80bB@j0V0VzS_@n1
IcVUEV>F0QR=:jecbP7]5l1
VDg1SIo80bB@j0V0VzS_@n1
R0
w1718968242
8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/db/myaltpll_altpll.v
FC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/db/myaltpll_altpll.v
!i122 0
L0 31 79
OV;L;2020.1;71
r1
!s85 0
31
!s108 1738765832.000000
!s107 C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/db/myaltpll_altpll.v|
!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/db|C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/db/myaltpll_altpll.v|
!i113 1
o-vlog01compat -work work
!s92 -vlog01compat -work work {+incdir+C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/db}
tCvgOpt 0
nmy@alt@pll_altpll
Euser
Z13 w1721323036
Z14 DPx9 altera_mf 20 altera_mf_components 0 22 HVLmIbRl@QhXfWVOmhK<j1
Z15 DPx3 lpm 14 lpm_components 0 22 jlWe>e^2@cAI7EQaRX2E;1
Z16 DPx4 ieee 11 numeric_std 0 22 aU^R8eGcicLcUFIaBQSL>3
R2
R3
!i122 1
R0
Z17 8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/fpga-user.vhd
Z18 FC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/fpga-user.vhd
l0
L9 1
VWf<QCh`HecWI3nn:fD==o2
!s100 `FAOGm1TCW;d^[U`NPmKD1
R6
31
R7
!i10b 1
R8
Z19 !s90 -reportprogress|300|-93|-work|work|C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/fpga-user.vhd|
Z20 !s107 C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/fpga-user.vhd|
!i113 1
R11
R12
Abehavioural
R14
R15
R16
R2
R3
DEx4 work 4 user 0 22 Wf<QCh`HecWI3nn:fD==o2
!i122 1
l68
L31 88
V8QDF[ZDA:5>TP_j]^LfoD3
!s100 59Ln8:XKoMKn5m9AHYQSB2
R6
31
R7
!i10b 1
R8
R19
R20
!i113 1
R11
R12
Euser_vhd_tst
Z21 w1721391647
R14
R15
R2
R3
!i122 3
R0
Z22 8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/simulation/modelsim/user.vht
Z23 FC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/simulation/modelsim/user.vht
l0
L35 1
VZ:[YOiZL75BVjB^J[z0fo2
!s100 ZV0eV_9QZ7UWgARJmdbS33
R6
31
Z24 !s110 1738765836
!i10b 1
Z25 !s108 1738765836.000000
Z26 !s90 -reportprogress|300|-93|-work|work|C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/simulation/modelsim/user.vht|
!s107 C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/simulation/modelsim/user.vht|
!i113 1
R11
R12
Auser_arch
R14
R15
R2
R3
DEx4 work 12 user_vhd_tst 0 22 Z:[YOiZL75BVjB^J[z0fo2
!i122 3
l73
L37 328
VgFBnn5]OPzI1]iY:@n[TW0
!s100 EbRJPzEVOYmQ5:C;0hcgg1
R6
31
R24
!i10b 1
R25
R26
Z27 !s107 C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/simulation/modelsim/user.vht|
!i113 1
R11
R12
