# Reading pref.tcl
# do fpga-user_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap work rtl_work 
# Copying C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlib SPI_Avalon_System
# ** Warning: (vlib-34) Library already exists at "SPI_Avalon_System".
# vmap SPI_Avalon_System SPI_Avalon_System
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap SPI_Avalon_System SPI_Avalon_System 
# Modifying modelsim.ini
# vlog -vlog01compat -work SPI_Avalon_System +incdir+C:/Users/Gianfranco\ Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules {C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SPI_Avalon_System_mm_interconnect_0.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:30:31 on Feb 05,2025
# vlog -reportprogress 300 -vlog01compat -work SPI_Avalon_System "+incdir+C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules" C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SPI_Avalon_System_mm_interconnect_0.v 
# -- Compiling module SPI_Avalon_System_mm_interconnect_0
# 
# Top level modules:
# 	SPI_Avalon_System_mm_interconnect_0
# End time: 15:30:32 on Feb 05,2025, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work SPI_Avalon_System +incdir+C:/Users/Gianfranco\ Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules {C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SPI_Avalon_System_onchip_memory2_0.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:30:32 on Feb 05,2025
# vlog -reportprogress 300 -vlog01compat -work SPI_Avalon_System "+incdir+C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules" C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SPI_Avalon_System_onchip_memory2_0.v 
# -- Compiling module SPI_Avalon_System_onchip_memory2_0
# 
# Top level modules:
# 	SPI_Avalon_System_onchip_memory2_0
# End time: 15:30:32 on Feb 05,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/Gianfranco\ Sarcia/Desktop/SPI_Avalon/fpga-user/db {C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/db/myaltpll_altpll.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:30:32 on Feb 05,2025
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/db" C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/db/myaltpll_altpll.v 
# -- Compiling module myAltPll_altpll
# 
# Top level modules:
# 	myAltPll_altpll
# End time: 15:30:32 on Feb 05,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv -work SPI_Avalon_System +incdir+C:/Users/Gianfranco\ Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules {C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/altera_merlin_slave_translator.sv}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:30:32 on Feb 05,2025
# vlog -reportprogress 300 -sv -work SPI_Avalon_System "+incdir+C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules" C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/altera_merlin_slave_translator.sv 
# -- Compiling module altera_merlin_slave_translator
# 
# Top level modules:
# 	altera_merlin_slave_translator
# End time: 15:30:32 on Feb 05,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv -work SPI_Avalon_System +incdir+C:/Users/Gianfranco\ Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules {C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/altera_merlin_master_translator.sv}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:30:32 on Feb 05,2025
# vlog -reportprogress 300 -sv -work SPI_Avalon_System "+incdir+C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules" C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/altera_merlin_master_translator.sv 
# -- Compiling module altera_merlin_master_translator
# 
# Top level modules:
# 	altera_merlin_master_translator
# End time: 15:30:33 on Feb 05,2025, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vcom -93 -work SPI_Avalon_System {C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/SPI_Avalon_System.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:30:33 on Feb 05,2025
# vcom -reportprogress 300 -93 -work SPI_Avalon_System C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/SPI_Avalon_System.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package LPM_COMPONENTS
# -- Loading package altera_mf_components
# -- Compiling entity SPI_Avalon_System
# -- Compiling architecture rtl of SPI_Avalon_System
# End time: 15:30:33 on Feb 05,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work SPI_Avalon_System {C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/Counter8_32.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:30:33 on Feb 05,2025
# vcom -reportprogress 300 -93 -work SPI_Avalon_System C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/Counter8_32.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity Counter8_32
# -- Compiling architecture Behavior of Counter8_32
# End time: 15:30:34 on Feb 05,2025, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vcom -93 -work SPI_Avalon_System {C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/FSM_Slave_SPI_to_Avalon.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:30:34 on Feb 05,2025
# vcom -reportprogress 300 -93 -work SPI_Avalon_System C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/FSM_Slave_SPI_to_Avalon.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity FSM_Slave_SPI_to_Avalon
# -- Compiling architecture Structure of FSM_Slave_SPI_to_Avalon
# End time: 15:30:34 on Feb 05,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work SPI_Avalon_System {C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/PISO.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:30:34 on Feb 05,2025
# vcom -reportprogress 300 -93 -work SPI_Avalon_System C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/PISO.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity PISO
# -- Compiling architecture behavior of PISO
# End time: 15:30:34 on Feb 05,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work SPI_Avalon_System {C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SIPO.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:30:34 on Feb 05,2025
# vcom -reportprogress 300 -93 -work SPI_Avalon_System C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SIPO.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity SIPO
# -- Compiling architecture Behaviour of SIPO
# End time: 15:30:35 on Feb 05,2025, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/fpga-user.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:30:35 on Feb 05,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/fpga-user.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package LPM_COMPONENTS
# -- Loading package altera_mf_components
# -- Compiling entity user
# -- Compiling architecture behavioural of user
# End time: 15:30:35 on Feb 05,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/myaltpll.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:30:35 on Feb 05,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/myaltpll.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity myAltPll
# -- Compiling architecture SYN of myaltpll
# End time: 15:30:35 on Feb 05,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work SPI_Avalon_System {C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/edge_detector.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:30:35 on Feb 05,2025
# vcom -reportprogress 300 -93 -work SPI_Avalon_System C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/edge_detector.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity Edge_detector
# -- Compiling architecture EdgeDetector_rtl of Edge_detector
# -- Loading entity SIPO
# End time: 15:30:35 on Feb 05,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work SPI_Avalon_System {C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/DP_Slave_SPI_to_Avalon.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:30:35 on Feb 05,2025
# vcom -reportprogress 300 -93 -work SPI_Avalon_System C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/DP_Slave_SPI_to_Avalon.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity DP_Slave_SPI_to_Avalon
# -- Compiling architecture arch of DP_Slave_SPI_to_Avalon
# -- Loading entity SIPO
# -- Loading entity PISO
# -- Loading package NUMERIC_STD
# -- Loading entity Counter8_32
# -- Loading entity Edge_detector
# End time: 15:30:36 on Feb 05,2025, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vcom -93 -work SPI_Avalon_System {C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SPI_Avalon_Component.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:30:36 on Feb 05,2025
# vcom -reportprogress 300 -93 -work SPI_Avalon_System C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SPI_Avalon_Component.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity SPI_Avalon_Component
# -- Compiling architecture rtl of SPI_Avalon_Component
# -- Loading entity DP_Slave_SPI_to_Avalon
# -- Loading entity FSM_Slave_SPI_to_Avalon
# End time: 15:30:36 on Feb 05,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/simulation/modelsim/user.vht}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:30:36 on Feb 05,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/simulation/modelsim/user.vht 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package LPM_COMPONENTS
# -- Loading package altera_mf_components
# -- Compiling entity user_vhd_tst
# -- Compiling architecture user_arch of user_vhd_tst
# End time: 15:30:36 on Feb 05,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -L SPI_Avalon_System -voptargs="+acc"  user_vhd_tst
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -L SPI_Avalon_System -voptargs=""+acc"" user_vhd_tst 
# Start time: 15:30:36 on Feb 05,2025
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading lpm.lpm_components
# Loading altera_mf.altera_mf_components
# Loading work.user_vhd_tst(user_arch)
# Loading ieee.numeric_std(body)
# Loading work.user(behavioural)
# Loading work.myaltpll(syn)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.mf_pllpack(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading altera_mf.altpll(behavior)
# Loading altera_mf.mf_cycloneiii_pll(vital_pll)
# Loading altera_mf.mf_cda_mn_cntr(behave)
# Loading altera_mf.mf_cda_scale_cntr(behave)
# Loading SPI_Avalon_System.spi_avalon_system(rtl)
# Loading SPI_Avalon_System.spi_avalon_component(rtl)
# Loading SPI_Avalon_System.dp_slave_spi_to_avalon(arch)
# Loading SPI_Avalon_System.sipo(behaviour)
# Loading SPI_Avalon_System.piso(behavior)
# Loading SPI_Avalon_System.counter8_32(behavior)
# Loading SPI_Avalon_System.edge_detector(edgedetector_rtl)
# Loading SPI_Avalon_System.fsm_slave_spi_to_avalon(structure)
# Loading SPI_Avalon_System.SPI_Avalon_System_onchip_memory2_0
# Loading altera_mf_ver.altsyncram
# Loading altera_mf_ver.altsyncram_body
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading altera_mf_ver.ALTERA_MF_MEMORY_INITIALIZATION
# Loading SPI_Avalon_System.SPI_Avalon_System_mm_interconnect_0
# Loading sv_std.std
# Loading SPI_Avalon_System.altera_merlin_master_translator
# Loading SPI_Avalon_System.altera_merlin_slave_translator
# ** Warning: (vsim-8683) Uninitialized out port /user_vhd_tst/i1/mcuUartRx has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized inout port /user_vhd_tst/i1/mcuI2cSda has no driver.
# This port will contribute value (U) to the signal network.
# 
# add wave *
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
#           File in use by: Gianfranco  Hostname: DESKTOP-VUSV08Q  ProcessID: 17848
#           Attempting to use alternate WLF file "./wlft0jvhdy".
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
#           Using alternate file: ./wlft0jvhdy
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run 300 us
# ** Note: Cyclone 10 LP PLL was reset
#    Time: 75 ns  Iteration: 2  Instance: /user_vhd_tst/i1/myAltPll_inst/altpll_component/CYCLONEIII_ALTPLL/M5
add wave -position insertpoint sim:/user_vhd_tst/i1/system/*
add wave -position insertpoint sim:/user_vhd_tst/i1/system/spi_avalon_component_0/*
add wave -position insertpoint sim:/user_vhd_tst/i1/system/onchip_memory2_0/*
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# ** Warning: (vsim-8683) Uninitialized out port /user_vhd_tst/i1/mcuUartRx has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized inout port /user_vhd_tst/i1/mcuI2cSda has no driver.
# This port will contribute value (U) to the signal network.
run
# GetModuleFileName: Impossibile trovare il modulo specificato.
# 
# 
# ** Note: Cyclone 10 LP PLL was reset
#    Time: 75 ns  Iteration: 2  Instance: /user_vhd_tst/i1/myAltPll_inst/altpll_component/CYCLONEIII_ALTPLL/M5
run
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# ** Warning: (vsim-8683) Uninitialized out port /user_vhd_tst/i1/mcuUartRx has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized inout port /user_vhd_tst/i1/mcuI2cSda has no driver.
# This port will contribute value (U) to the signal network.
run
# GetModuleFileName: Impossibile trovare il modulo specificato.
# 
# 
# ** Note: Cyclone 10 LP PLL was reset
#    Time: 75 ns  Iteration: 2  Instance: /user_vhd_tst/i1/myAltPll_inst/altpll_component/CYCLONEIII_ALTPLL/M5
run
run
run
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# ** Warning: (vsim-8683) Uninitialized out port /user_vhd_tst/i1/mcuUartRx has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized inout port /user_vhd_tst/i1/mcuI2cSda has no driver.
# This port will contribute value (U) to the signal network.
run
# GetModuleFileName: Impossibile trovare il modulo specificato.
# 
# 
# ** Note: Cyclone 10 LP PLL was reset
#    Time: 75 ns  Iteration: 2  Instance: /user_vhd_tst/i1/myAltPll_inst/altpll_component/CYCLONEIII_ALTPLL/M5
run
run
add wave -position insertpoint sim:/user_vhd_tst/i1/system/onchip_memory2_0/*
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/system/onchip_memory2_0/INIT_FILE
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# ** Warning: (vsim-8683) Uninitialized out port /user_vhd_tst/i1/mcuUartRx has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized inout port /user_vhd_tst/i1/mcuI2cSda has no driver.
# This port will contribute value (U) to the signal network.
run
# GetModuleFileName: Impossibile trovare il modulo specificato.
# 
# 
# ** Note: Cyclone 10 LP PLL was reset
#    Time: 75 ns  Iteration: 2  Instance: /user_vhd_tst/i1/myAltPll_inst/altpll_component/CYCLONEIII_ALTPLL/M5
run
run
# End time: 19:03:56 on Feb 05,2025, Elapsed time: 3:33:20
# Errors: 0, Warnings: 2
