m255
K4
z2
!s11e MIXED_VERSIONS
!s11f vlog 2020.1 2020.02, Feb 28 2020
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 dC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/simulation/modelsim
vhard_block
Z1 !s110 1720891906
!i10b 1
!s100 Z9EN1cgOKV0J54^@e3nYT3
Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1
IYLjcM54[eFA@li6ICM4J51
Z3 VDg1SIo80bB@j0V0VzS_@n1
R0
Z4 w1720891894
Z5 8fpga-user.vo
Z6 Ffpga-user.vo
!i122 0
L0 7462 29
Z7 OV;L;2020.1;71
r1
!s85 0
31
Z8 !s108 1720891906.000000
Z9 !s107 fpga-user.vo|
Z10 !s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+.|fpga-user.vo|
!i113 1
Z11 o-vlog01compat -work work
Z12 !s92 -vlog01compat -work work +incdir+.
Z13 tCvgOpt 0
vuser
R1
!i10b 1
!s100 I?WD9^MdEib0=EP>nbkP:2
R2
Ie:I7@=;ICMGCd3aIVDlXJ2
R3
R0
R4
R5
R6
!i122 0
L0 32 7429
R7
r1
!s85 0
31
R8
R9
R10
!i113 1
R11
R12
R13
Euser_vhd_tst
Z14 w1720716694
Z15 DPx9 altera_mf 20 altera_mf_components 0 22 HVLmIbRl@QhXfWVOmhK<j1
Z16 DPx3 lpm 14 lpm_components 0 22 jlWe>e^2@cAI7EQaRX2E;1
Z17 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
Z18 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
!i122 1
R0
Z19 8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/simulation/modelsim/user.vht
Z20 FC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/simulation/modelsim/user.vht
l0
L35 1
VZ:[YOiZL75BVjB^J[z0fo2
!s100 ZV0eV_9QZ7UWgARJmdbS33
Z21 OV;C;2020.1;71
31
R1
!i10b 1
R8
Z22 !s90 -reportprogress|300|-93|-work|work|C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/simulation/modelsim/user.vht|
!s107 C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/simulation/modelsim/user.vht|
!i113 1
Z23 o-93 -work work
Z24 tExplicit 1 CvgOpt 0
Auser_arch
R15
R16
R17
R18
DEx4 work 12 user_vhd_tst 0 22 Z:[YOiZL75BVjB^J[z0fo2
!i122 1
l73
L37 336
VB_k1O1TG>4QRg1M:@GO`D1
!s100 NDE0:eUPW?iHk0J9@6@bn1
R21
31
R1
!i10b 1
R8
R22
Z25 !s107 C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/simulation/modelsim/user.vht|
!i113 1
R23
R24
