m255
K4
z2
!s11e MIXED_VERSIONS
!s11f vlog 2020.1 2020.02, Feb 28 2020
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 dC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/simulation/modelsim
valtera_merlin_master_translator
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IfInbmE2YFN05F<iERM@^M2
Z4 VDg1SIo80bB@j0V0VzS_@n1
S1
R0
w1718967705
8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/altera_merlin_master_translator.sv
FC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/altera_merlin_master_translator.sv
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L0 32 525
Z5 OV;L;2020.1;71
r1
!s85 0
31
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!i113 1
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Z9 tCvgOpt 0
valtera_merlin_slave_translator
R1
Z10 !s110 1738765832
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R3
I<IzzmP^?j>:1Z:J?di^9c3
R4
S1
R0
w1721390452
8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/altera_merlin_slave_translator.sv
FC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/altera_merlin_slave_translator.sv
!i122 1609
L0 35 448
R5
r1
!s85 0
31
R6
!s107 C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/altera_merlin_slave_translator.sv|
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!i113 1
R7
R8
R9
valtera_reset_controller
Z11 !s110 1720891020
!i10b 1
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R3
IkncE;Yzeom^VNZz9?ko^P2
R4
R0
w1719337000
8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/altera_reset_controller.v
FC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/altera_reset_controller.v
!i122 972
L0 42 278
R5
r1
!s85 0
31
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!i113 1
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R9
valtera_reset_synchronizer
R11
!i10b 1
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R3
ITSoJ;6Ih]^mXe[HNE=52N2
R4
R0
w1719336986
8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/altera_reset_synchronizer.v
FC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/altera_reset_synchronizer.v
!i122 973
L0 24 63
R5
r1
!s85 0
31
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!i113 1
R12
R13
R9
Ecode_decoder
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R0
Z17 8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/Code_Decoder.vhd
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l0
L4 1
V@NFn79Ua_3hT3Vc8c5H`I1
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!i113 1
Z24 o-93 -work SPI_Avalon_System
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Abehavioral
R15
R16
DEx4 work 12 code_decoder 0 22 @NFn79Ua_3hT3Vc8c5H`I1
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l16
L14 28
V@R`nbEfnHHQdnJ]KZi5he2
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R19
31
R20
!i10b 1
R21
R22
R23
!i113 1
R24
R25
Ecounter8_32
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R15
R16
!i122 1612
R0
Z28 8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/Counter8_32.vhd
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l0
L5 1
VgFB1be5z35P_BIinBMaBB1
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R19
31
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!i10b 1
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!i113 1
R24
R25
Abehavior
R27
R15
R16
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l19
L15 27
VdjX0DE_BoXC77I<@nF8]U3
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R19
31
R30
!i10b 1
R31
R32
R33
!i113 1
R24
R25
Edp_slave_spi_to_avalon
Z35 w1721323488
R15
R16
!i122 1617
R0
Z36 8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/DP_Slave_SPI_to_Avalon.vhd
Z37 FC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/DP_Slave_SPI_to_Avalon.vhd
l0
L5 1
Vl63^kV1zKd^JaALe[6OHj3
!s100 l9IAijoflf1[?lD19iYiS3
R19
31
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!i10b 1
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!i113 1
R24
R25
Aarch
Z42 DEx4 work 13 edge_detector 0 22 `5[26ah<gdoo9ZBI6BZSH3
R27
R34
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R15
R16
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!i122 1617
l40
L36 73
VNJCXSVk`@N:>Y]0k;9R9_2
!s100 4mJD]A0^:^f;VzWTzN0=U2
R19
31
R38
!i10b 1
R39
R40
R41
!i113 1
R24
R25
Eedge_detector
Z46 w1721215945
R15
R16
!i122 1616
R0
Z47 8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/edge_detector.vhd
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l0
L4 1
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R19
31
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!i10b 1
R39
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!i113 1
R24
R25
Aedgedetector_rtl
R44
R15
R16
R42
!i122 1616
l21
L17 20
VhnZYeS8K]Q0CFA`lejUPm2
!s100 ;4ze;4Y2[OXSi9B<?_[F_1
R19
31
R49
!i10b 1
R39
R50
R51
!i113 1
R24
R25
Efsm_slave_spi_to_avalon
Z52 w1721390833
R27
R15
R16
!i122 1613
R0
Z53 8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/FSM_Slave_SPI_to_Avalon.vhd
Z54 FC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/FSM_Slave_SPI_to_Avalon.vhd
l0
L4 1
Vz6`=4YaN2ofkGACNSama<3
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R19
31
R30
!i10b 1
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!i113 1
R24
R25
Astructure
R27
R15
R16
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!i122 1613
l45
L35 501
VU1]zhe_53gjzzTFBM]H6e0
!s100 AfH8UMUAzmK@G6XWmEQ`I3
R19
31
R30
!i10b 1
R55
R56
R57
!i113 1
R24
R25
Episo
Z59 w1718972419
R15
R16
!i122 1614
R0
Z60 8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/PISO.vhd
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l0
L4 1
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!s100 ZMK>n<3h4;Qka;N=6k5Z<3
R19
31
R30
!i10b 1
R55
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!i113 1
R24
R25
Abehavior
R15
R16
R43
!i122 1614
l17
L16 29
VK9hKaaoL^2G`5l<LRA_fW0
!s100 gNSB^7I9?RjRKA>X@LP4n2
R19
31
R30
!i10b 1
R55
R62
R63
!i113 1
R24
R25
Esipo
Z64 w1721154104
R15
R16
!i122 1615
R0
Z65 8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SIPO.vhd
Z66 FC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SIPO.vhd
l0
L5 1
V6iV^;hklGMLn7@^c<Sc:Y2
!s100 ]ERPGoQNPX?;NmDSQkVXk3
R19
31
R49
!i10b 1
R55
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!i113 1
R24
R25
Abehaviour
R15
R16
R44
!i122 1615
l19
L15 84
VSmh0bU:dVgC`1Y:33Yiia0
!s100 a4GEQ92M0?N;SCNi:kD@E2
R19
31
R49
!i10b 1
R55
R67
R68
!i113 1
R24
R25
Espi_avalon_component
Z69 w1721323383
R27
R15
R16
!i122 1618
R0
Z70 8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SPI_Avalon_Component.vhd
Z71 FC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SPI_Avalon_Component.vhd
l0
L15 1
VBlQDJB>caQmTbB_cI<BB13
!s100 oORV:R]E<YdGT`F=z5L?R2
R19
31
R38
!i10b 1
Z72 !s108 1738765836.000000
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!i113 1
R24
R25
Artl
R58
R45
R27
R15
R16
Z75 DEx4 work 20 spi_avalon_component 0 22 BlQDJB>caQmTbB_cI<BB13
!i122 1618
l54
Z76 L33 85
Z77 Ve>LE<<gKmD71WNb3I8cHm1
Z78 !s100 @JI8VS2=<`O7S>Q0EO]6X2
R19
31
R38
!i10b 1
R72
R73
R74
!i113 1
R24
R25
Espi_avalon_system
Z79 w1721323037
Z80 DPx9 altera_mf 20 altera_mf_components 0 22 HVLmIbRl@QhXfWVOmhK<j1
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R27
R15
R16
!i122 1611
R0
Z82 8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/SPI_Avalon_System.vhd
Z83 FC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/SPI_Avalon_System.vhd
l0
L14 1
Vf9Q8AK^7P<XVVhMNXoYFc3
!s100 bbNWoH08<N_7VJ0GKzg9R0
R19
31
R2
!i10b 1
R31
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Z85 !s107 C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/SPI_Avalon_System.vhd|
!i113 1
R24
R25
Artl
R80
R81
R27
R15
R16
DEx4 work 17 spi_avalon_system 0 22 f9Q8AK^7P<XVVhMNXoYFc3
!i122 1611
l98
L26 129
VZ59]PQTeC[]cJYiEiB5Wj2
!s100 I]G4_[7]T_zo?FO4cc>]^1
R19
31
R2
!i10b 1
R31
R84
R85
!i113 1
R24
R25
vSPI_Avalon_System_mm_interconnect_0
R10
!i10b 1
!s100 ;OiZE6j7R:8hTC2k>HzI=0
R3
I>nXd?JX5cQo]BAEjLhZhn2
R4
R0
w1721301843
8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SPI_Avalon_System_mm_interconnect_0.v
FC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SPI_Avalon_System_mm_interconnect_0.v
!i122 1607
L0 9 155
R5
r1
!s85 0
31
!s108 1738765831.000000
!s107 C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SPI_Avalon_System_mm_interconnect_0.v|
!s90 -reportprogress|300|-vlog01compat|-work|SPI_Avalon_System|+incdir+C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules|C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SPI_Avalon_System_mm_interconnect_0.v|
!i113 1
R12
R13
R9
n@s@p@i_@avalon_@system_mm_interconnect_0
vSPI_Avalon_System_onchip_memory2_0
R10
!i10b 1
!s100 8T^]jWFUfiPV]LLaJK7`<1
R3
IlDc42oV]i68^4@3fGoh>K3
R4
R0
w1721301842
8C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SPI_Avalon_System_onchip_memory2_0.v
FC:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SPI_Avalon_System_onchip_memory2_0.v
!i122 1608
L0 21 84
R5
r1
!s85 0
31
R6
!s107 C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SPI_Avalon_System_onchip_memory2_0.v|
!s90 -reportprogress|300|-vlog01compat|-work|SPI_Avalon_System|+incdir+C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules|C:/Users/Gianfranco Sarcia/Desktop/SPI_Avalon/fpga-user/SPI_Avalon_System/synthesis/submodules/SPI_Avalon_System_onchip_memory2_0.v|
!i113 1
R12
R13
R9
n@s@p@i_@avalon_@system_onchip_memory2_0
