
State Machine - |user|SPI_Avalon_System:system|SPI_Avalon_Component:spi_avalon_component_0|FSM_Slave_SPI_to_Avalon:Control_Unit|present_state
Name present_state.s19_wait7_rd present_state.s18_wait6_rd present_state.s17_send_data present_state.s16_wait5_rd present_state.s15_read_data present_state.s14_wait4_rd present_state.s13_wait3_rd present_state.s12_wait5_wr present_state.s11_write_mem present_state.s10_wait5_wr present_state.s9_data_samp present_state.s8_wait4_wr present_state.s7_wait3_wr present_state.s6_address_samp present_state.s5_wait_2 present_state.s4_wait_1 present_state.s3_opcode_samp present_state.s2_sclk present_state.s1_idle present_state.s0_reset 
present_state.s0_reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
present_state.s1_idle 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
present_state.s2_sclk 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
present_state.s3_opcode_samp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
present_state.s4_wait_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
present_state.s5_wait_2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
present_state.s6_address_samp 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
present_state.s7_wait3_wr 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
present_state.s8_wait4_wr 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
present_state.s9_data_samp 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
present_state.s10_wait5_wr 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
present_state.s11_write_mem 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
present_state.s12_wait5_wr 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s13_wait3_rd 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s14_wait4_rd 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s15_read_data 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s16_wait5_rd 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s17_send_data 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s18_wait6_rd 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s19_wait7_rd 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
