# Reading pref.tcl
# do fpga-user_run_msim_rtl_vhdl.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap work rtl_work 
# Copying C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/Trigger.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:31 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/Trigger.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity TRIGGER
# -- Compiling architecture Behaviour of TRIGGER
# End time: 18:37:32 on Feb 27,2025, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/PIPO32bit.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:32 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/PIPO32bit.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity PIPO32bit
# -- Compiling architecture Behavioral of PIPO32bit
# End time: 18:37:32 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/mux_16_to_1.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:32 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/mux_16_to_1.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity mux_16_to_1
# -- Compiling architecture Behavioral of mux_16_to_1
# End time: 18:37:32 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/mux_2_to_1_vector.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:32 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/mux_2_to_1_vector.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity mux_2_to_1_vector
# -- Compiling architecture Behavioral of mux_2_to_1_vector
# End time: 18:37:32 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/mux_2_to_1.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:32 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/mux_2_to_1.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity mux_2_to_1
# -- Compiling architecture Behavioral of mux_2_to_1
# End time: 18:37:32 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/memory.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:32 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/memory.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity memory
# -- Compiling architecture beh of memory
# End time: 18:37:32 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/Loop_Management.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:32 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/Loop_Management.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity Loop_Management
# -- Compiling architecture behaviour of Loop_Management
# End time: 18:37:32 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/DP_Glitch_Detector.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:32 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/DP_Glitch_Detector.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity DP_Glitch_Detector
# -- Compiling architecture behaviour of DP_Glitch_Detector
# End time: 18:37:32 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/CU_Logic_Analyzer.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:32 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/CU_Logic_Analyzer.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity CU_Logic_Analyzer
# -- Compiling architecture Structure of CU_Logic_Analyzer
# End time: 18:37:33 on Feb 27,2025, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/CU_Glitch_Detector.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:33 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/CU_Glitch_Detector.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity CU_Glitch_Detector
# -- Compiling architecture Structure of CU_Glitch_Detector
# End time: 18:37:33 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/Clock_Generator.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:33 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/Clock_Generator.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity Clock_Generator
# -- Compiling architecture behaviour of Clock_Generator
# End time: 18:37:33 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/ADDR_Manager.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:33 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/ADDR_Manager.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity ADDR_Manager
# -- Compiling architecture behaviour of ADDR_Manager
# End time: 18:37:33 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/SPI_to_Avalon/SIPO.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:33 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/SPI_to_Avalon/SIPO.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity SIPO
# -- Compiling architecture Behaviour of SIPO
# End time: 18:37:33 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/SPI_to_Avalon/PISO.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:33 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/SPI_to_Avalon/PISO.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity PISO
# -- Compiling architecture behavior of PISO
# End time: 18:37:33 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/SPI_to_Avalon/FSM_Slave_SPI_to_Avalon.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:33 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/SPI_to_Avalon/FSM_Slave_SPI_to_Avalon.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity FSM_Slave_SPI_to_Avalon
# -- Compiling architecture Structure of FSM_Slave_SPI_to_Avalon
# End time: 18:37:33 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/SPI_to_Avalon/Counter8_32.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:34 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/SPI_to_Avalon/Counter8_32.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity Counter8_32
# -- Compiling architecture Behavior of Counter8_32
# End time: 18:37:34 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/fpga-user.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:34 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/fpga-user.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package LPM_COMPONENTS
# -- Loading package altera_mf_components
# -- Compiling entity user
# -- Compiling architecture behavioural of user
# End time: 18:37:34 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/Glitch_Detector.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:34 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/Glitch_Detector.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity Glitch_Detector
# -- Compiling architecture behaviour of Glitch_Detector
# -- Loading entity DP_Glitch_Detector
# -- Loading entity CU_Glitch_Detector
# End time: 18:37:34 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/SPI_to_Avalon/edge_detector.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:34 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/SPI_to_Avalon/edge_detector.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity Edge_detector
# -- Compiling architecture EdgeDetector_rtl of Edge_detector
# -- Loading entity SIPO
# End time: 18:37:34 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/Glitch_Detector_32Bit.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:34 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/Glitch_Detector_32Bit.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity Glitch_Detector_32Bit
# -- Compiling architecture structure of Glitch_Detector_32Bit
# -- Loading entity Glitch_Detector
# End time: 18:37:34 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/SPI_to_Avalon/DP_Slave_SPI_to_Avalon.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:34 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/SPI_to_Avalon/DP_Slave_SPI_to_Avalon.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity DP_Slave_SPI_to_Avalon
# -- Compiling architecture arch of DP_Slave_SPI_to_Avalon
# -- Loading entity SIPO
# -- Loading entity PISO
# -- Loading package NUMERIC_STD
# -- Loading entity Counter8_32
# -- Loading entity Edge_detector
# End time: 18:37:34 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/DP_Logic_Analyzer.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:34 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/DP_Logic_Analyzer.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity DP_Logic_analyzer
# -- Compiling architecture structure of DP_Logic_analyzer
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading entity PIPO32bit
# -- Loading package NUMERIC_STD
# -- Loading entity Clock_Generator
# -- Loading entity mux_2_to_1
# -- Loading entity mux_2_to_1_vector
# -- Loading entity ADDR_Manager
# -- Loading entity Glitch_Detector_32Bit
# -- Loading entity memory
# -- Loading entity mux_16_to_1
# -- Loading entity TRIGGER
# -- Loading entity Loop_Management
# End time: 18:37:35 on Feb 27,2025, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/SPI_to_Avalon/SPI_Avalon_Component.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:35 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/SPI_to_Avalon/SPI_Avalon_Component.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity SPI_Avalon_Component
# -- Compiling architecture rtl of SPI_Avalon_Component
# -- Loading entity DP_Slave_SPI_to_Avalon
# -- Loading entity FSM_Slave_SPI_to_Avalon
# End time: 18:37:35 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/Logic_Analyzer.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:35 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer/Logic_Analyzer.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity Logic_Analyzer
# -- Compiling architecture structure of Logic_Analyzer
# -- Loading entity DP_Logic_analyzer
# -- Loading package NUMERIC_STD
# -- Loading entity CU_Logic_Analyzer
# End time: 18:37:35 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer_System.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:35 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/vhdl_files/Logic_Analyzer_System.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity Logic_Analyzer_System
# -- Compiling architecture structure of Logic_Analyzer_System
# -- Loading entity Logic_Analyzer
# -- Loading entity SPI_Avalon_Component
# End time: 18:37:35 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vcom -93 -work work {C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/simulation/modelsim/user.vht}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:37:35 on Feb 27,2025
# vcom -reportprogress 300 -93 -work work C:/Users/Gianfranco Sarcia/Desktop/Logic_Analyzer_IP_User/fpga-user/simulation/modelsim/user.vht 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity user_vhd_tst
# -- Compiling architecture user_arch of user_vhd_tst
# End time: 18:37:35 on Feb 27,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclone10lp -L rtl_work -L work -voptargs="+acc"  user_vhd_tst
# vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclone10lp -L rtl_work -L work -voptargs=""+acc"" user_vhd_tst 
# Start time: 18:37:35 on Feb 27,2025
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading work.user_vhd_tst(user_arch)
# Loading ieee.numeric_std(body)
# Loading lpm.lpm_components
# Loading altera_mf.altera_mf_components
# Loading work.user(behavioural)
# Loading work.logic_analyzer_system(structure)
# Loading work.logic_analyzer(structure)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.dp_logic_analyzer(structure)
# Loading work.pipo32bit(behavioral)
# Loading work.clock_generator(behaviour)
# Loading work.mux_2_to_1(behavioral)
# Loading work.mux_2_to_1_vector(behavioral)
# Loading work.addr_manager(behaviour)
# Loading work.glitch_detector_32bit(structure)
# Loading work.glitch_detector(behaviour)
# Loading work.dp_glitch_detector(behaviour)
# Loading work.cu_glitch_detector(structure)
# Loading work.memory(beh)
# Loading work.mux_16_to_1(behavioral)
# Loading work.trigger(behaviour)
# Loading work.loop_management(behaviour)
# Loading work.cu_logic_analyzer(structure)
# Loading work.spi_avalon_component(rtl)
# Loading work.dp_slave_spi_to_avalon(arch)
# Loading work.sipo(behaviour)
# Loading work.piso(behavior)
# Loading work.counter8_32(behavior)
# Loading work.edge_detector(edgedetector_rtl)
# Loading work.fsm_slave_spi_to_avalon(structure)
# ** Warning: (vsim-8683) Uninitialized out port /user_vhd_tst/i1/mcuUartRx has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized inout port /user_vhd_tst/i1/mcuI2cSda has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8684) No drivers exist on out port /user_vhd_tst/i1/leds(3 downto 2), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /user_vhd_tst/leds(3 downto 2).
# 
# add wave *
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
#           File in use by: Gianfranco  Hostname: DESKTOP-VUSV08Q  ProcessID: 900
#           Attempting to use alternate WLF file "./wlft8q3dqd".
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
#           Using alternate file: ./wlft8q3dqd
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run 1 sec
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/LOOP_MANAGEMENT
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/CLOCK_GENERATOR
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/clock_sink_clk
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/reset_sink_reset
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/mosi
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/miso
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/ss
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/sclk
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/done
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/leds(0)
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/error
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/en_miso
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/read_data
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/RAM_MEMORY/address
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/RAM_MEMORY/memory
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/CU_LOGIC_ANALYZER/setting
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/CU_LOGIC_ANALYZER/rd
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/SPI_Avalon_Component/Sh_data_read_i
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/SPI_Avalon_Component/wr_i
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/SPI_Avalon_Component/avalon_master_writedata
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/SPI_Avalon_Component/Sh_data_write_i
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/SPI_Avalon_Component/Sh_address_i
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/SPI_Avalon_Component/Sh_Command_i
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# ** Warning: (vsim-8683) Uninitialized out port /user_vhd_tst/i1/mcuUartRx has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized inout port /user_vhd_tst/i1/mcuI2cSda has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8684) No drivers exist on out port /user_vhd_tst/i1/leds(3 downto 2), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /user_vhd_tst/leds(3 downto 2).
run -all
# GetModuleFileName: Impossibile trovare il modulo specificato.
# 
# 
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/LOOP_MANAGEMENT
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/CLOCK_GENERATOR
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/reset
force -freeze sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/reset 0 0
# ** Warning: (vsim-8780) Forcing /user_vhd_tst/i1/rst as root of /user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/reset specified in the force.
add wave -position insertpoint  \
sim:/user_vhd_tst/lsasBus
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# ** Warning: (vsim-8683) Uninitialized out port /user_vhd_tst/i1/mcuUartRx has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized inout port /user_vhd_tst/i1/mcuI2cSda has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8684) No drivers exist on out port /user_vhd_tst/i1/leds(3 downto 2), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /user_vhd_tst/leds(3 downto 2).
force -freeze sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/reset 1 0
# ** Warning: (vsim-8780) Forcing /user_vhd_tst/i1/rst as root of /user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/reset specified in the force.
run
# GetModuleFileName: Impossibile trovare il modulo specificato.
# 
# 
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/LOOP_MANAGEMENT
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/CLOCK_GENERATOR
run
run
run
force -freeze sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/reset 0 0
# ** Warning: (vsim-8780) Forcing /user_vhd_tst/i1/rst as root of /user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/reset specified in the force.
run -all
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/RAM_MEMORY/WR
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# ** Warning: (vsim-8683) Uninitialized out port /user_vhd_tst/i1/mcuUartRx has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized inout port /user_vhd_tst/i1/mcuI2cSda has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8684) No drivers exist on out port /user_vhd_tst/i1/leds(3 downto 2), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /user_vhd_tst/leds(3 downto 2).
run
# GetModuleFileName: Impossibile trovare il modulo specificato.
# 
# 
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/LOOP_MANAGEMENT
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/CLOCK_GENERATOR
run -all
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# ** Warning: (vsim-8683) Uninitialized out port /user_vhd_tst/i1/mcuUartRx has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized inout port /user_vhd_tst/i1/mcuI2cSda has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8684) No drivers exist on out port /user_vhd_tst/i1/leds(3 downto 2), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /user_vhd_tst/leds(3 downto 2).
run
# GetModuleFileName: Impossibile trovare il modulo specificato.
# 
# 
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/LOOP_MANAGEMENT
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/CLOCK_GENERATOR
run
force -freeze sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/reset 0 0
# ** Warning: (vsim-8780) Forcing /user_vhd_tst/i1/rst as root of /user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/reset specified in the force.
run -all
add wave -position insertpoint  \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/RAM_Glitch/memory(16) \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/RAM_Glitch/memory(17) \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/RAM_Glitch/memory(18) \
sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/RAM_Glitch/memory(19)
restart
restart
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# ** Warning: (vsim-8683) Uninitialized out port /user_vhd_tst/i1/mcuUartRx has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized inout port /user_vhd_tst/i1/mcuI2cSda has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8684) No drivers exist on out port /user_vhd_tst/i1/leds(3 downto 2), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /user_vhd_tst/leds(3 downto 2).
run
# GetModuleFileName: Impossibile trovare il modulo specificato.
# 
# 
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/LOOP_MANAGEMENT
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/DP_LOGIC_ANALYZER/CLOCK_GENERATOR
force -freeze sim:/user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/reset 0 0
# ** Warning: (vsim-8780) Forcing /user_vhd_tst/i1/rst as root of /user_vhd_tst/i1/Logic_Analyzer_Sys/Logic_Analyzer/reset specified in the force.
run -all
run -all
# End time: 19:10:49 on Feb 27,2025, Elapsed time: 0:33:14
# Errors: 0, Warnings: 6
