
State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|SPI_Avalon_Component:SPI_Avalon_Component|FSM_Slave_SPI_to_Avalon:Control_Unit|present_state
Name present_state.s19_wait7_rd present_state.s18_wait6_rd present_state.s17_send_data present_state.s16_wait5_rd present_state.s15_read_data present_state.s14_wait4_rd present_state.s13_wait3_rd present_state.s12_wait5_wr present_state.s11_write_mem present_state.s10_wait5_wr present_state.s9_data_samp present_state.s8_wait4_wr present_state.s7_wait3_wr present_state.s6_address_samp present_state.s5_wait_2 present_state.s4_wait_1 present_state.s3_opcode_samp present_state.s2_sclk present_state.s1_idle present_state.s0_reset 
present_state.s0_reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
present_state.s1_idle 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
present_state.s2_sclk 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
present_state.s3_opcode_samp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
present_state.s4_wait_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
present_state.s5_wait_2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
present_state.s6_address_samp 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
present_state.s7_wait3_wr 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
present_state.s8_wait4_wr 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
present_state.s9_data_samp 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
present_state.s10_wait5_wr 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
present_state.s11_write_mem 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
present_state.s12_wait5_wr 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s13_wait3_rd 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s14_wait4_rd 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s15_read_data 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s16_wait5_rd 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s17_send_data 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s18_wait6_rd 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s19_wait7_rd 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|CU_Logic_Analyzer:CU_LOGIC_ANALYZER|present_state
Name present_state.s31_enable_addr_manager present_state.s30_reset_addr_loop present_state.s29_wait_clock_sample present_state.s27_1_addr_loop_first present_state.s27_addr_loop_upgrade present_state.s26_error present_state.s25_done present_state.s24_sample_writing present_state.s23_wait_clock_sample present_state.s22_glitch_manager present_state.s21_trigger_value present_state.s20_trigger_active present_state.s19_loop_active present_state.s18_divider_check present_state.s17_6_wait present_state.s17_5_update_address present_state.s17_4_update_loop present_state.s17_3_enable_read_reg present_state.s17_2_loop_read_first present_state.s17_1_rd_glitch present_state.s17_rd_glitch present_state.s16_7_reset_address_manager present_state.s16_6_wait present_state.s16_5_update_address present_state.s16_4_update_loop present_state.s16_3_enable_read_reg present_state.s16_2_loop_read_first present_state.s16_1_rd_samples present_state.s16_rd_samples present_state.s15_rd_max_loop_reg present_state.s14_wr_max_loop_reg present_state.s13_rd_working_mode_reg present_state.s12_wr_working_mode_reg present_state.s11_rd_trigger_condition_reg present_state.s10_wr_trigger_condition_reg present_state.s9_rd_trigger_mask_reg present_state.s8_wr_trigger_mask_reg present_state.s7_rd_addr_reg present_state.s6_1_enable_addr_manager present_state.s6_wr_addr_reg present_state.s5_rd_clock_selection_reg present_state.s4_wr_clock_selection_reg present_state.s3_rd_clock_divider_reg present_state.s2_wr_clock_divider_reg present_state.s1_idle present_state.s0_reset 
present_state.s0_reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
present_state.s1_idle 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
present_state.s2_wr_clock_divider_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
present_state.s3_rd_clock_divider_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
present_state.s4_wr_clock_selection_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
present_state.s5_rd_clock_selection_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
present_state.s6_wr_addr_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
present_state.s6_1_enable_addr_manager 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
present_state.s7_rd_addr_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
present_state.s8_wr_trigger_mask_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
present_state.s9_rd_trigger_mask_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
present_state.s10_wr_trigger_condition_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
present_state.s11_rd_trigger_condition_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s12_wr_working_mode_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s13_rd_working_mode_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s14_wr_max_loop_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s15_rd_max_loop_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s16_rd_samples 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s16_1_rd_samples 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s16_2_loop_read_first 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s16_3_enable_read_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s16_4_update_loop 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s16_5_update_address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s16_6_wait 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s16_7_reset_address_manager 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s17_rd_glitch 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s17_1_rd_glitch 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s17_2_loop_read_first 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s17_3_enable_read_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s17_4_update_loop 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s17_5_update_address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s17_6_wait 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s18_divider_check 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s19_loop_active 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s20_trigger_active 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s21_trigger_value 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s22_glitch_manager 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s23_wait_clock_sample 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s24_sample_writing 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s25_done 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s26_error 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s27_addr_loop_upgrade 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s27_1_addr_loop_first 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s29_wait_clock_sample 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s30_reset_addr_loop 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s31_enable_addr_manager 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_31|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_30|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_29|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_28|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_27|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_26|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_25|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_24|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_23|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_22|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_21|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_20|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_19|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_18|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_17|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_16|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_15|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_14|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_13|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_12|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_11|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_10|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_9|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_8|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_7|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_6|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_5|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_4|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_3|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_2|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_1|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 

State Machine - |user|Logic_Analyzer_System:Logic_Analyzer_Sys|Logic_Analyzer:Logic_Analyzer|DP_Logic_analyzer:DP_LOGIC_ANALYZER|Glitch_Detector_32Bit:GLITCH_DETECTOR|Glitch_Detector:Glitch_BIT_0|CU_Glitch_Detector:CU_Glitch|present_state
Name present_state.s4_wait present_state.s3_glitch present_state.s2_one present_state.s1_zero present_state.s0_idle 
present_state.s0_idle 0 0 0 0 0 
present_state.s1_zero 0 0 0 1 1 
present_state.s2_one 0 0 1 0 1 
present_state.s3_glitch 0 1 0 0 1 
present_state.s4_wait 1 0 0 0 1 
