
State Machine - |user|Pattern_Generator_System:Pattern_Generator_Sys|SPI_Avalon_Component:SPI_Avalon_Component|FSM_Slave_SPI_to_Avalon:Control_Unit|present_state
Name present_state.s19_wait7_rd present_state.s18_wait6_rd present_state.s17_send_data present_state.s16_wait5_rd present_state.s15_read_data present_state.s14_wait4_rd present_state.s13_wait3_rd present_state.s12_wait5_wr present_state.s11_write_mem present_state.s10_wait5_wr present_state.s9_data_samp present_state.s8_wait4_wr present_state.s7_wait3_wr present_state.s6_address_samp present_state.s5_wait_2 present_state.s4_wait_1 present_state.s3_opcode_samp present_state.s2_sclk present_state.s1_idle present_state.s0_reset 
present_state.s0_reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
present_state.s1_idle 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
present_state.s2_sclk 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
present_state.s3_opcode_samp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
present_state.s4_wait_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
present_state.s5_wait_2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
present_state.s6_address_samp 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
present_state.s7_wait3_wr 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
present_state.s8_wait4_wr 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
present_state.s9_data_samp 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
present_state.s10_wait5_wr 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
present_state.s11_write_mem 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
present_state.s12_wait5_wr 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s13_wait3_rd 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s14_wait4_rd 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s15_read_data 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s16_wait5_rd 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s17_send_data 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s18_wait6_rd 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s19_wait7_rd 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |user|Pattern_Generator_System:Pattern_Generator_Sys|Pattern_Generator:Pattern_Generator|CU_Pattern_Generator:CONTROL_UNITY|present_state
Name present_state.s35_upgrade_register present_state.s34_rd_data_memory present_state.s33_wr_data_on_memory present_state.s32_1_update_addr_write_memory present_state.s32_update_addr_write_memory present_state.s31_error present_state.s30_done present_state.s29_1_update_addr_loop present_state.s29_update_addr_loop present_state.s28_generate_pattern present_state.s27_wait_clock_sample present_state.s26_trigger_value present_state.s25_trigger_active present_state.s24_memory_active present_state.s23_loop_active present_state.s22_divider_check present_state.s21_rd_max_loop_reg present_state.s20_wr_max_loop_reg present_state.s19_rd_mask_OE_reg present_state.s18_wr_mask_OE_reg present_state.s17_rd_working_mode_reg present_state.s16_wr_working_mode_reg present_state.s15_rd_start_reg present_state.s14_wr_start_reg present_state.s13_rd_trigger_condition_reg present_state.s12_wr_trigger_condition_reg present_state.s11_rd_trigger_mask_reg present_state.s10_wr_trigger_mask_reg present_state.s9_rd_data_reg present_state.s8_wr_data_reg present_state.s7_rd_addr_reg present_state.s6_wr_addr_reg present_state.s5_rd_clock_selection_reg present_state.s4_wr_clock_selection_reg present_state.s3_rd_clock_divider_reg present_state.s2_wr_clock_divider_reg present_state.s1_idle present_state.s0_reset 
present_state.s0_reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
present_state.s1_idle 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
present_state.s2_wr_clock_divider_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
present_state.s3_rd_clock_divider_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
present_state.s4_wr_clock_selection_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
present_state.s5_rd_clock_selection_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
present_state.s6_wr_addr_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
present_state.s7_rd_addr_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
present_state.s8_wr_data_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
present_state.s9_rd_data_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
present_state.s10_wr_trigger_mask_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
present_state.s11_rd_trigger_mask_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
present_state.s12_wr_trigger_condition_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s13_rd_trigger_condition_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s14_wr_start_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s15_rd_start_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s16_wr_working_mode_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s17_rd_working_mode_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s18_wr_mask_OE_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s19_rd_mask_OE_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s20_wr_max_loop_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s21_rd_max_loop_reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s22_divider_check 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s23_loop_active 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s24_memory_active 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s25_trigger_active 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s26_trigger_value 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s27_wait_clock_sample 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s28_generate_pattern 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s29_update_addr_loop 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s29_1_update_addr_loop 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s30_done 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s31_error 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s32_update_addr_write_memory 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s32_1_update_addr_write_memory 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s33_wr_data_on_memory 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s34_rd_data_memory 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
present_state.s35_upgrade_register 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
