Hierarchy | Input | Constant Input | Unused Input | Floating Input | Output | Constant Output | Unused Output | Floating Output | Bidir | Constant Bidir | Unused Bidir | Input only Bidir | Output only Bidir
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
system|mm_interconnect_0|onchip_memory2_0_s1_translator | 115 | 7 | 22 | 7 | 83 | 7 | 7 | 7 | 0 | 0 | 0 | 0 | 0
system|mm_interconnect_0|spi_avalon_component_0_avalon_master_translator | 116 | 17 | 0 | 17 | 108 | 17 | 17 | 17 | 0 | 0 | 0 | 0 | 0
system|mm_interconnect_0 | 100 | 0 | 0 | 0 | 82 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
system|onchip_memory2_0|the_altsyncram|auto_generated | 49 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
system|onchip_memory2_0 | 53 | 2 | 1 | 2 | 32 | 2 | 2 | 2 | 0 | 0 | 0 | 0 | 0
system|spi_avalon_component_0|Control_Unit | 10 | 0 | 0 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
system|spi_avalon_component_0|Datapath|Synchronization_Serial_Clock|Synchronization | 5 | 30 | 0 | 30 | 32 | 30 | 30 | 30 | 0 | 0 | 0 | 0 | 0
system|spi_avalon_component_0|Datapath|Synchronization_Serial_Clock | 5 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
system|spi_avalon_component_0|Datapath|Counter_Bits | 3 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
system|spi_avalon_component_0|Datapath|Data_Read_Register | 36 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
system|spi_avalon_component_0|Datapath|Data_Write_Register | 5 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
system|spi_avalon_component_0|Datapath|Address_Register | 5 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
system|spi_avalon_component_0|Datapath|Command_Register | 5 | 24 | 0 | 24 | 32 | 24 | 24 | 24 | 0 | 0 | 0 | 0 | 0
system|spi_avalon_component_0|Datapath | 47 | 0 | 0 | 0 | 71 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
system|spi_avalon_component_0 | 38 | 0 | 0 | 0 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
system | 5 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
myAltPll_inst|altpll_component|auto_generated | 3 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
myAltPll_inst | 2 | 2 | 0 | 2 | 2 | 2 | 2 | 2 | 0 | 0 | 0 | 0 | 0