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Reliability Analysis of Convolutional Neural Network through Soft Error Mitigation Controller

Manuel Capaccio

Reliability Analysis of Convolutional Neural Network through Soft Error Mitigation Controller.

Rel. Luca Sterpone, Sarah Azimi. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023

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The progresses of Deep Neural Networks (DNNs) in several disciplines like image processing, system monitoring and decision making, continue to accelerate, making them appealing for space applications, in particular if implemented on SRAM-based FPGAs, which offer several advantages, like low cost manufacturing, CPUs-like performance and field programmability. Therefore, radiation effects have to be considered in design phase. Ionizing particles can modify the state of gates in electronic devices, leading to permanent faults (Hard Errors) or temporary ones (Soft Errors). Single Event Upsets (SEU), one kind of soft error, can modify the value of one or more bits stored in the FPGA configuration memory, potentially causing design failures. It is therefore important to be able to easily and cheaply verify the behavior of the design subjected to SEUs so as to be able to mitigate their effects if needed. In this Thesis the Xilinx Essential Bits technology and the capabilities of the Soft Error Mitigation (SEM) Controller, an IP developed by Xilinx, are exploited to perform fast and cheap fault injection campaigns to simulate SEUs and to deeply analyze the behaviour of a single convolutional neuron, implemented in the programmable logic of the Xilinx System on Chip Zynq XC7Z020. The neuron belongs to the input layers of the ZFNet Convolutional Network present in the Alpha Data CNN Library. Critical sections of the neuron architecture are identified and then mitigated with a selective Triple Modular Redundancy (TMR) to reduce resources overhead. Finally, the ZFNet input layers with the modified neuron in them are submitted to a fault injection campaign to understand if the mitigation results obtained for a small block of a redundant architecture, such as DNNs, where several neurons are present, are propagated to the entire design.

Relators: Luca Sterpone, Sarah Azimi
Academic year: 2023/24
Publication type: Electronic
Number of Pages: 91
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/29451
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