Politecnico di Torino (logo)

Low power implementation of neural network extension for RISC-V CPU

Dario Lo Presti Costantino

Low power implementation of neural network extension for RISC-V CPU.

Rel. Danilo Demarchi. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023

PDF (Tesi_di_laurea) - Tesi
Licenza: Creative Commons Attribution Non-commercial No Derivatives.

Download (13MB) | Preview

Deep Learning and Neural Networks have been studied and developed for many years as of today, but there is still a great need of research on this field, because the industry needs are rapidly changing. The new challenge in this field is called edge inference and it is the deployment of Deep Learning on small, simple and cheap devices, such as low power microcontrollers. At the same time, also on the field of hardware design the industry is moving towards the RISC-V micro-architecture, which is open-source and is developing at such a fast rate that it will become soon the standard. ONiO operates in this framework, and its chip, ONiO.zero, is a batteryless ultra low power microcontroller based on energy harvesting and RISC-V microarchitecture. The challenge on which this project is based is to make a simple Neural Network work on this chip, i.e. finding out the capabilities and the limits of this chip for such an application and trying to optimize as much as possible the power and energy consumption. To do that TensorFlow Lite Micro has been chosen as Deep Learning framework of reference, and a simple existing application was studied and tested first on the SparkFun Edge board and then successfully ported to the RISC-V ONiO.zero core, with its restrictive features. The optimizations have been done on the convolutional layer of the neural network, both by Software, implementing the Im2col algorithm, and by Hardware, designing and implementing a new RISC-V instruction and the corresponding Hardware unit that performs four 8-bit parallel multiply-and-accumulate operations. This new design drastically reduces the inference time of 4 times, meaning XX less instructions executed, meaning lower overall power consumption. This kind of application on this kind of chip can open the doors to a whole new market, giving the possibility to have thousands small, cheap and self-sufficient chips deploying Deep Learning applications to solve simple everyday life problems, even without network connection and without any privacy issue.

Relators: Danilo Demarchi
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 127
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: KTH - Kungl. Tekniska Hogskolan (Royal Institute of Technology) (SVEZIA)
Aziende collaboratrici: ONiO AS
URI: http://webthesis.biblio.polito.it/id/eprint/26929
Modify record (reserved for operators) Modify record (reserved for operators)