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Gate-All-Around FET: analytical compact modeling and TCAD validation for system performance evaluation

Silvio Gucciardo

Gate-All-Around FET: analytical compact modeling and TCAD validation for system performance evaluation.

Rel. Marco Vacca, Fabrizio Mo. Politecnico di Torino, Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict), 2023

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Integrated electronics industry, since early 70s, realized how increasing the transistors integration density was the key to push towards the performances in CMOS technology. The notorious Moore’s law chronicled, for almost fifty years, the evolution of chip industry. The main strategy to improve switching frequency, power dissipation and area was typically the constant field scaling approach traced out by Dennard et al. at IBM in 1974 which was based on keeping the electric field constant by scaling down device geometry and supply voltage by a constant factor to keep reliability unaltered and improving current capability. In more aggressively scaled nodes the short channel effects (SCE) compromised the feasibility of this approach leading to unbearable subthreshold leakage in planar MOSFETs. Multi-gate transistor technology soon became the most relevant solution to keep pushing the Moore’s law and to mitigate SCEs. In the first part of this work the industry state-of-the-art double-gate MOSFET (DG-MOSFET) analytical model has been studied solving numerically the Poisson’s equation inside the channel for intrinsic and doped substrate using the perturbation approach. Accurate electrostatic potential and charge density solution together with short channel effects correction allowed to extract accurate I-V and C-V curves which allowed to develop a compact model which has been validated with physical-based device simulations (TCAD) in channel pinch-off and velocity saturation conditions. The simulations show a good matching even without process-specific fitting parameters with a maximum error of 30% above threshold in the I-V output characteristics up to Lg=13nm. In the second part of the work, the same approach has been applied to a possible candidate for high-density logic and memory applications: the cylindrical gate-All-Around FET (cy-GAAFET). An analytical model has been developed solving the Poisson’s equation self-consistently with the gate bias equation. The model predicts the behavior of the potential inside the channel for intrinsic and doped substrate. Also, SCEs corrections has been included to follow the current degradation. Accurate I-V and C-V curves have been extracted and validated with TCAD. The cylindrical GAAFET model shows better results compared to the DG-MOSFET's one at the same gate length because of the better electrostatic control the surrounding gate has on the channel, which limits the short channel effects that are more difficult to be fitted without empirical parameters. Fitting parameters can be extracted from physical-based simulations to reduce the error, especially in above-threshold region, where the short channel effects are less severe. The built compact models, thanks to the evaluation of the potential profile inside the device, are well-suited for system performance evaluation simulators, such as TAMTAMS (previously developed at Politecnico di Torino).

Relators: Marco Vacca, Fabrizio Mo
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 64
Corso di laurea: Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: Politecnico di Torino
URI: http://webthesis.biblio.polito.it/id/eprint/26737
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