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Optimization of NS-GAAFET technology through low-κ dielectrics for spacer fabrication

Antonio Colonna

Optimization of NS-GAAFET technology through low-κ dielectrics for spacer fabrication.

Rel. Gianluca Piccinini, Fabrizio Mo, Chiara Elfi Spano. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023

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Over the years, the manufacturing technology and structure of transistors has had continuous development. The channel length dimension has steadily decreased and the number of transistors per chip has steadily increased. With the scaling and the considerable increase in the number of transistors, problems related to power consumption, transistor speed, interconnection delays and the achievement of channel lengths of a few nanometers problems such as the short channel effect (SCE) have had to be faced. If the technological breakthrough of the last decade is represented by the Finfet which has made it possible to solve many problems thanks to the use of a 3D technology, the next step is represented by the GAAFET, Gate All Around Field Effect Transistor. GAAFET technology with greater electrostatic control allowed scaling beyond 5 nm. Unlike the Finfet, the spacer structure of the GAAFET is more complicated by having the inner spacers, dielectric material between the nanosheets to avoid short circuits between the gate and source and drain. In the thesis there is an overview of the GAAFET manufacturing processes focusing on the fabrication of the inner spacers which represent a fundamental and delicate step. With the aim of improving the performance of GAAFETs, low dielectric constant(κ) materials have been analyzed. By implementing the low-κ materials both in the frontend-of-line and in the back-end-of-line it is possible to reduce the parasitic capacitances and consequently mainly reduce the power consumption and the RC delay. In the More Moore chapter of IRDS 2022 it is predicted that the value of κ for spacers may reach 2.7 in 2034. In the first phase, a research analysis of low dielectric constant materials was conducted. The different types of materials, the mechanisms to further reduce the value of κ and the main problems were analysed. It has been deduced that polymers are the materials which have low dielectric constant and in general one can reduce the dielectric constant of a material through the creation of pores. Low-κ materials have poor mechanical properties and this represents the major obstacle in implementation with current transistor fabrication processes. Among the possible low-κ materials, the study of polytetrafluoroethylene (PTFE), a polymer with a κ value of about 2, was undertaken. Through the use of atomistic simulation software, QuantumATK, the main electrical and thermomechanical properties were simulated. In particular, the dielectric tensor, the glass transition temperature, the Young’s modulus and the Poisson’s ratio have been simulated. In using this material as a dielectric for the GAAFETs, the focus is on the FEOL and in particular on the use as a spacer material. The use of the Sentaurus software made it possible to simulate the GAAFET manufacturing processes and to check the performance of the device obtained. Then PTFE was introduced as a spacer material and through the simulation of the different parameters that characterize the performance of a transistor, the benefits of using a low-κ material were found. Polymers represent a new frontier in their use as dielectric materials in transistors. Continuous research is needed into the perfect dielectric to be compatible with fabrication processes.

Relators: Gianluca Piccinini, Fabrizio Mo, Chiara Elfi Spano
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 91
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: Politecnico di Torino
URI: http://webthesis.biblio.polito.it/id/eprint/26734
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