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i.MX95 Performance and Functional Verification

Edoardo Rolfo

i.MX95 Performance and Functional Verification.

Rel. Claudio Passerone, Daniele Antonioli. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023


HW DIGITAL DESIGN VERIFICATION - IMX9 VERIFICATION ENVIRONMENT AND PERFORMANCE AND INTERCONNECTION Functional and performance verification have an important role in IoT and Embedded system world. The former covers the base functional correctness and the latter the respect of constraint limits. A good verification process ensures that a product will work based on its original design and an internal check is performed to make sure it follows its initial design specification. Verification environment has a key role in production process as it provides a former analysis of the design through diversified tests, giving a detailed report about the effects on the design, highlighting flaws and potential problems: it allows scientists to see if their product performs as intended and also any unforeseen side effects that it may have. Monetary and time cost the company will incur to fix the issue will be minimized if a deviation from the original design specification is caught early in the life cycle of the product. The integration of performance features inside Proxy environment (used for functional verification) is compliant with the verification procedure and represent a possible upgrade of the existing tool adding new features, to guarantee automation and ease-of-use. The first part of the thesis deals with the basis of the verification process, with a focus on different techniques and scopes, and analyzing in details the UVM methodology and its flow. The second part present an analysis of the two environment under investigation (functional and performance), highlighting the similarities and differences. This will lead to a strategy to merge the two environments in one tool and proposing a new flow for Performance verification. The last part shows the results and improvements achieved with this new flow, showing the advantages and the existing problematics still open. Some of them will be addressed to researchers and developers that desires to extend the exposed integration.

Relators: Claudio Passerone, Daniele Antonioli
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 80
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: NXP Semiconductors France SAS
URI: http://webthesis.biblio.polito.it/id/eprint/26690
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