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Power evaluation for Non-volatile memories testing in safety critical automotive Soc

Francesca Sanna

Power evaluation for Non-volatile memories testing in safety critical automotive Soc.

Rel. Paolo Bernardi. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022


The tests aim at identifying and compensate process variation or fabrication issue. If a compensation is not possible, then it is important to identify and discard failing devices as soon as possible not to waste time (and consequently money) on useless devices. The tests especially suffer from voltage droops when it is performed at critical voltages values. It is crucial to mitigate this voltage droops that can cause false fails during the test of the DUTs. This is especially true if the amplitude of the droop is enough to bring the power supply below what is called the Vfail voltage, overcoming the guard band set by the manufacturer Fig. ??. To overcome the voltage droops, two different strategies have been developed in this thesis . The first make use of a partially integrated Embedded Voltage Regulator (EVR) while the second uses an external circuit. Both approaches raises the supply voltage just before the critical steps known to be sources of voltage droops. The supply voltage is then lowered again to continue the test at the minimum supply voltage set by the manufacturers. During their tests manufacturers adopt a complete array of measurement devices. Having a stable and reliable setup is essential as is fundamental to guarantee the repeatability of the measurements. During production and characterization, one of the main tests for Automotive SoC is called Voltage sweep, a stress test aimed to evaluate the behavior of the DUT at the variation of the supply voltage. The absolute maximum and minimum voltage values are determined by observing the correctness of the results of a given set of operations that can range from memory read/write to logic computations. Of course these tests are fundamental to characterize a device performance and, especially for the lower voltage values, power consumption. Manufacturers actually test their devices in harsher conditions than the one recommended for the final users, to retain a certain safety margin. During the characterization phase, a minimum voltage called Vmin is chosen. Vmin is chosen considering a Guard band that allow the device to work even if a voltage droop is present and it is equal to Vfail + Guard band. The Soc have a minimum and a maximum operating voltage specifications. If the voltage droop exceed the minimum threshold the device no longer give reliable results. The droop are caused by a high dynamic power consumption depending on the instructions that are executed. When this happens the device requires large amount of current for brief period from the power source. 1 There is a strict correlation between a rapid requirement of current and voltage droops . Current spikes are usually caused by a strong activity inside the devices, like activating more than one CPU in parallel or performing steps such as the PLL lock. The current spikes cause a discharge of the decoupling capacitors and when the charge decreases, according to the formula V = QC , also the voltage inside the capacitors decreases. This event occurs in a really short time that the power supply is not able to compensate, so it has a strong effect on the voltage causing the droops

Relators: Paolo Bernardi
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 26
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: Infineon Technologies AG
URI: http://webthesis.biblio.polito.it/id/eprint/25524
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