Politecnico di Torino (logo)

Evaluating the cell-aware fault coverage of functional test programs

Iacopo Guglielminetti

Evaluating the cell-aware fault coverage of functional test programs.

Rel. Matteo Sonza Reorda, Michelangelo Grosso, Riccardo Cantoro. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2022

PDF (Tesi_di_laurea) - Tesi
Licenza: Creative Commons Attribution Non-commercial No Derivatives.

Download (5MB) | Preview

Testing an integrated circuit (IC) is the process aiming at identifying faulty products that do not behave according to specifications. During the fabrication of IC, physical defects could arise. Since physical defects are difficult to work with, logical faults have been created. The way a logical fault models a physical defect is called fault model. After creating a fault model, the testing flow continues with fault detection with a fault simulator. When the fault is present in a model, it creates a misbehaviour observable on the outputs. To perform fault detection we need to apply tests on the unit under test. For years many models were proposed: bridge, stuck-at-faults, transition, N-detect, timing-aware, and layout-aware are just an example. Also, a recent new model was created, the cell-aware test (CAT). The CAT fault model is the main focus of this thesis. This model was developed to satisfy the growing demand for more precise faults models. IC manufacturers in the last years discover that many of the integrated circuits that escape the post-production test have intra-cell defects that the normal faults models are not able to represent, like stack-at faults. CAT aims at creating a fault model able to completely represent the defects for every cell of a synthesis library, in particular, this model represents 3 kinds of intra-cell defects: transistor defects, open defects and short defects. The thesis aims at creating a working flow for testing IC with CAT faults. The designs taken into consideration range from small circuits to a processor. The flow starts from a synthesis library. For every cell of it, it creates a model with CAT faults. Then a fault simulation using CAT faults is performed. The input files used are the design synthesized with the library, a list of faults created by a tool precisely develop for CAT faults and input patterns to simulate. The inputs pattern are in a different format. The kind of tests performed on the IC is mainly 2, functional testing and structural, or “scan,” test. At last, the flow created is compared with another existing one to convalidate the results, also some checks by hand are made on a very small IC. In conclusion, this thesis presents the results of a new testing flow, made with the CAT faults model and a fault simulator able to handle it. The results will be on small and large IC and then will be compared with another existing flow. The flow will be used for functional testing and scan testing.

Relators: Matteo Sonza Reorda, Michelangelo Grosso, Riccardo Cantoro
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 144
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING
Aziende collaboratrici: STMicroelectronics
URI: http://webthesis.biblio.polito.it/id/eprint/25512
Modify record (reserved for operators) Modify record (reserved for operators)