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Compiler to generate RTL from Spec for Power Management System

Pierfrancesco Antonio Boccardi

Compiler to generate RTL from Spec for Power Management System.

Rel. Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022


Nowadays, people working in electronic engineering companies are often involved in different projects at same time. Therefore, there are two possible ways to complete required tasks in the scheduled time: enlarging the team, so that the large amount of work can be split among more people, or allocating more time for each project. Obviously, each company aims to optimize the available resources, engaging a limited number of people in the same project and avoiding to allocate too much time just for one step in the design flow. Generally, time-to-market is an important aspect for the companies, to beat the competitors and maximize sales. It means that most of the times, the tape-out date is fixed and can not be delayed for any reason. As a consequence, it is important to allocate proper time for each step in the design flow, considering that sometimes coming back to previous steps to fix some problems can be required. For these reasons, time turns out to be a precious and very limited resource, to handle in the best possible way. Therefore, if some time might be saved somewhere, it should be done, so that more complex tasks could be relaxed or the tape-out date could be moved up. In this direction, one possible solution could be limiting the effort to perform the easiest tasks that usually do not involve problem-solving skills. These tasks are usually the most boring part of the work and in some cases might be really time-consuming. For this aim, software tools can be helpful. They are, of course, more suitable for this kind of work, since they are able to do it faster and in a more efficient way, if they are properly designed. In the ASIC design flow, they could be used to convert some input specifications in RTL code, so that the hardware designers can be relieved from the repetitive and mundane work, and can focus on more complex tasks. For sure, more work can be automated, less effort will be required to digital designers to perform those tasks, limited just to define the input specifications required to auto-generate the design. This Master Thesis project was developed during my internship in Qualcomm, and it is focused on a compiler, a software tool that aims to generate RTL code starting from input specifications. In particular, since the team in which I took part was involved in developing and maintaining the Power Management System integrated on every Qualcomm chip, this compiler was developed to help the team during the design of this Hard Macro.

Relators: Maurizio Martina
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 105
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: Qualcomm (IRLANDA)
Aziende collaboratrici: Qualcomm
URI: http://webthesis.biblio.polito.it/id/eprint/25493
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