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Improving write patterns performance in a Cached Memory System

Vlad George Bancila

Improving write patterns performance in a Cached Memory System.

Rel. Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022


High-performance processors support a write streaming mode: a write-on-miss policy intended to optimize both performance and power-savings when writing large blocks of data. The goal of this work is to study ways to improve the streaming mode in a Cached Memory System to enhance the overall energy efficiency of a pipelined, superscalar and out-of-order Arm processor. Preliminary investigations with a software model of the CPU show the distribution of the writing patterns exhibited by benchmark suites and the performance of the state-of-the-art streaming mode, illustrating how wrong decisions in data streaming could lead to higher backpressure from the core of the CPU. The investigations are then used as a compass to drive the designing phase of the work in which three different solutions are discussed. Moreover, two different prediction mechanisms are developed to support the streaming mode in covering writing scenarios that are here shown to typically arise in CPUs. Those solutions aim at increasing the volume of streamed data using different heuristics that exploit the properties of the incoming traffic into the Memory System. The prediction mechanisms are implemented both in the software model of the CPU and at Register Transfer Level. The modeling phase is useful to efficiently evaluate the coverage and the accuracy of the prediction while exploring the design space by tuning the parameters of the predictors. Finally, the impact on the performance of the CPU and the hardware cost of each solution is assessed, followed by some final considerations on the accomplished work.

Relators: Maurizio Martina
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 73
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: ARM France SAS
URI: http://webthesis.biblio.polito.it/id/eprint/25490
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