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Embedded Non-Volatile Memory BIST low-level API implementation to characterize and optimize production test throughput and read latency

Matteo Battilana

Embedded Non-Volatile Memory BIST low-level API implementation to characterize and optimize production test throughput and read latency.

Rel. Paolo Bernardi, Riccardo Cantoro, Alberto Rizzi, Massimo Giltrelli. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2022


Nowadays, the automotive industry is not only the most fruitful one in terms of revenue but it has the highest spending on the Research and Development, accordingly to a publication from Joint Research Centre (JRC), published in 2021. This has a strong influence on how the entire development process is structured, with special attention to apply the leading technologies. Moreover, the electronic components used in the automotive domain must guarantee a sufficiently high reliability. A product that has been designed to be sold in the mass market, just like a smartwatch for example, does not need the same level of dependability of an ABS (Anti-Break System) unit. Even if they both use microcontrollers, a failure in the smartwatch can reduce the availability and, in the worst case, totally make the device unusable. From the customer point of view, the worst situation that could happen is only a state of disapproval; on the other hand, a failure in a crucial unit in the safety-critical context could be the starting point of hazards. In order to achieve an adequately high reliability, the manufacturers have to spend a sufficient amount of time and person resources, both during and at the end of the production phase, in order to characterize the produced devices and to forecast their behaviours and the expected lifetime. In the automotive field, the majority of the area of a microcontroller is designated to the memory; the combination of the large portion used in the die, almost half of the total chip area, and the high integration density, poses a critical problem: the probability of a fault inside the memory array is not negligible. For this reason, the main efforts are focused on guaranteeing a sufficiently high reliability for the desired purpose. In order to achieve this goal, complex test algorithms have been designed and grouped in the so called "TestWare" term. The first part of the work that has been done, was focused on studying the design of current state-of-the-art product in development, the latest TriCore AURIX microcontroller. More precisely, the main focus was on a crucial hardware component that was already present in the previous microcontroller generation, called SSE (Screen Support Engine) that exploits the base approach of the Memory Built-In Self-Test (MBIST). Previous studies on this module have been replicated and checked, in order to be compliant with the current implementation that uses Flash memories as Non-Volatile Memories (NVM) and its interface, called Flash Standard Interface (FSI), used to communicate with them. Different scenarios and combinations have been studied, in order to sufficiently and exhaustively verify the current implementation and to understand the SSE behaviour. The second part of this thesis is based on the implementation and development of low-level APIs to interface the SSE module, that has been ported to a completely different hardware architecture that uses a new memory technology and so, different memory access paradigms. This part is not only related to the mere C implementation of the firmware but covers also the validation and verification of the SSE behaviour in this new NVM technology. Moreover, studies against the reading margins have been conducted in order to check that the CPU and SSE verification results are the same. Furthermore, being in the industrial field, the test time is fundamental and must be characterized; for this reason, an exhaustive timings evaluation has been conducted using the just developed code.

Relators: Paolo Bernardi, Riccardo Cantoro, Alberto Rizzi, Massimo Giltrelli
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 105
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING
Aziende collaboratrici: Infineon Technologies Italia S.r.l.
URI: http://webthesis.biblio.polito.it/id/eprint/24690
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